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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc>
185 lines
5.4 KiB
C
185 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/mbus.h>
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#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
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#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
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#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
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#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
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#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
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#define DS414_GPP_OUT_VAL_HIGH (0)
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#define DS414_GPP_OUT_POL_LOW (0)
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#define DS414_GPP_OUT_POL_MID (0)
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#define DS414_GPP_OUT_POL_HIGH (0)
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#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
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#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
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BIT(13) | BIT(14) | BIT(15)))
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#define DS414_GPP_OUT_ENA_HIGH (~0)
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static const u32 ds414_mpp_control[] = {
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0x11111111,
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0x22221111,
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0x22222222,
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0x00000000,
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0x11110000,
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0x00004000,
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0x00000000,
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0x00000000,
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0x00000000
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};
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/* DDR3 static MC configuration */
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/* 1G_v1 (4x2Gbits) adapted by DS414 */
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MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
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{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
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{0x00001404, 0x30000800}, /*Dunit Control Low Register */
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{0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
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{0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
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{0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
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{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
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{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
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{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
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{0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
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{0x00001428, 0x000F8830}, /*Dunit Control High Register */
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{0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
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{0x0000147C, 0x0000C671},
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{0x000014a0, 0x00000001},
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{0x000014a8, 0x00000100}, /*2:1 */
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{0x00020220, 0x00000006},
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{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
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{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
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{0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
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{0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
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{0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
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{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
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{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
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{0x0001504, 0x3FFFFFE1}, /* CS0 Size */
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{0x000150C, 0x00000000}, /* CS1 Size */
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{0x0001514, 0x00000000}, /* CS2 Size */
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{0x000151C, 0x00000000}, /* CS3 Size */
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{0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
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{0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
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{0x000015D0, 0x00000650}, /*MR0 */
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{0x000015D4, 0x00000044}, /*MR1 */
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{0x000015D8, 0x00000010}, /*MR2 */
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{0x000015DC, 0x00000000}, /*MR3 */
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{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
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{0x000015EC, 0xF800A225}, /*DDR PHY */
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{0x0, 0x0}
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};
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MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
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{"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
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};
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extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
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MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
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{ MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
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{ PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
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PEX_BUS_DISABLED },
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0x0040, serdes_change_m_phy
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}
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};
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MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
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{
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return &ds414_ddr_modes[0];
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}
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MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
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{
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return &ds414_serdes_cfg[0];
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}
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u8 board_sat_r_get(u8 dev_num, u8 reg)
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{
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return 0xf; /* All PEX ports support PCIe Gen2 */
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}
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int board_early_init_f(void)
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{
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int i;
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/* Set GPP Out value */
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reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
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reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
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reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
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/* set GPP polarity */
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reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
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reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
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reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
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/* Set GPP Out Enable */
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reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
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reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
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reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
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for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
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reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
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return 0;
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}
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int board_init(void)
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{
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u32 pwr_mng_ctrl_reg;
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* Gate unused clocks
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*
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* Note: Disabling unused PCIe lanes will hang PCI bus scan.
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* Once this is resolved, bits 10-12, 26 and 27 can be
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* unset here as well.
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*/
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pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
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pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
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pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
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pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
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pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
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pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
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pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
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pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
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reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: DS414\n");
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return 0;
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}
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