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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead, locked outer cache is used as RAM area during the early boot stage where DRAM is not ready yet. This effectively means MMU must be always enabled while we are in SPL. Currently, the SPL image for UniPhier SoCs contains the page table statically defined at compile time. It has been a burden because the 16KB page table occupies a quarter memory footprint of the 64KB SPL image. Finally, there is no more room to implement new features in SPL. Setting aside the NOR boot mode, this issue can be solved by creating the page table onto RAM at run time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
208 lines
5.8 KiB
ArmAsm
208 lines
5.8 KiB
ArmAsm
/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <linux/sizes.h>
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#include <asm/system.h>
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#include "ssc-regs.h"
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ENTRY(lowlevel_init)
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mov r8, lr @ persevere link reg across call
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/*
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* The UniPhier Boot ROM loads SPL code to the L2 cache.
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* But CPUs can only do instruction fetch now because start.S has
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* cleared C and M bits.
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* First we need to turn on MMU and Dcache again to get back
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* data access to L2.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_DEBUG_LL
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bl debug_ll_init
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#endif
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bl setup_init_ram @ RAM area for stack and page talbe
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/*
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* Now we are using the page table embedded in the Boot ROM.
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* It is not handy since it is not a straight mapped table for sLD3.
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* Also, the access to the external bus is prohibited. What we need
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* to do next is to create a page table and switch over to it.
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*/
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bl create_page_table
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bl v7_flush_dcache_all
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/* Disable MMU and Dcache before switching Page Table */
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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bl enable_mmu
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mov lr, r8 @ restore link
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mov pc, lr @ back to my caller
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ENDPROC(lowlevel_init)
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ENTRY(enable_mmu)
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mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
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bic r0, r0, #0x37
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orr r0, r0, #0x20 @ disable TTBR1
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mcr p15, 0, r0, c2, c0, 2
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orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
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mcr p15, 0, r0, c2, c0, 0 @ TTBR0
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mov r0, #-1 @ manager for all domains (No permission check)
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mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
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dsb
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isb
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/*
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* MMU on:
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* TLBs was already invalidated in "../start.S"
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* So, we don't need to invalidate it here.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr
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ENDPROC(enable_mmu)
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/*
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* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
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* It is large enough for tmp RAM.
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*/
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#define BOOT_RAM_SIZE (SZ_32K)
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#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
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#define BOOT_WAY_BITS (0x00000100) /* way 8 */
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ENTRY(setup_init_ram)
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/*
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* Touch to zero for the boot way
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*/
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0:
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/*
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* set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
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*/
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ldr r0, = 0x00408006 @ touch to zero with address range
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ldr r1, = SSCOQM
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str r0, [r1]
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ldr r0, = BOOT_RAM_BASE
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ldr r1, = SSCOQAD
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str r0, [r1]
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ldr r0, = BOOT_RAM_SIZE
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ldr r1, = SSCOQSZ
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str r0, [r1]
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ldr r0, = BOOT_WAY_BITS
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ldr r1, = SSCOQWN
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str r0, [r1]
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ldr r1, = SSCOPPQSEF
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ldr r0, [r1]
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cmp r0, #0 @ check if the command is successfully set
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bne 0b @ try again if an error occurs
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ldr r1, = SSCOLPQS
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1:
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ldr r0, [r1]
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cmp r0, #0x4
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bne 1b @ wait until the operation is completed
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str r0, [r1] @ clear the complete notification flag
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mov pc, lr
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ENDPROC(setup_init_ram)
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#define DEVICE 0x00002002 /* Non-shareable Device */
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#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
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ENTRY(create_page_table)
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ldr r0, = DEVICE
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ldr r1, = BOOT_RAM_BASE
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mov r12, r1 @ r12 is preserved during D-cache flush
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0: str r0, [r1], #4 @ specify all the sections as Device
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adds r0, r0, #0x00100000
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bcc 0b
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ldr r0, = NORMAL
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str r0, [r12] @ mark the first section as Normal
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add r0, r0, #0x00100000
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str r0, [r12, #4] @ mark the second section as Normal
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mov pc, lr
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ENDPROC(create_page_table)
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/* We don't use Thumb instructions for now */
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#define ARM(x...) x
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#define THUMB(x...)
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* - mm - mm_struct describing address space
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*
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* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
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*/
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ENTRY(v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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mov pc, lr
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ENDPROC(v7_flush_dcache_all)
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