mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 12:29:44 +09:00
6b0c26fa05
The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
||
|---|---|---|
| .. | ||
| aspeed | ||
| at91 | ||
| exynos | ||
| renesas | ||
| rockchip | ||
| tegra | ||
| uniphier | ||
| clk_bcm6345.c | ||
| clk_boston.c | ||
| clk_fixed_rate.c | ||
| clk_pic32.c | ||
| clk_sandbox_test.c | ||
| clk_sandbox.c | ||
| clk_stm32f.c | ||
| clk_stm32h7.c | ||
| clk_stm32mp1.c | ||
| clk_zynq.c | ||
| clk_zynqmp.c | ||
| clk-hsdk-cgu.c | ||
| clk-uclass.c | ||
| Kconfig | ||
| Makefile | ||