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76cff2b108
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* (C) Copyright 2015
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* Texas Instruments Incorporated
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*
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* Lokesh Vutla <lokeshvutla@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DRA7_IODELAY_H_
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#define _DRA7_IODELAY_H_
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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/* CONFIG_REG_0 */
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#define CFG_REG_0_OFFSET 0xC
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#define CFG_REG_ROM_READ_SHIFT 1
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#define CFG_REG_ROM_READ_MASK (1 << 1)
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#define CFG_REG_CALIB_STRT_SHIFT 0
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#define CFG_REG_CALIB_STRT_MASK (1 << 0)
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#define CFG_REG_CALIB_STRT 1
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#define CFG_REG_CALIB_END 0
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#define CFG_REG_ROM_READ_START (1 << 1)
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#define CFG_REG_ROM_READ_END (0 << 1)
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/* CONFIG_REG_2 */
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#define CFG_REG_2_OFFSET 0x14
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#define CFG_REG_REFCLK_PERIOD_SHIFT 0
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#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
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#define CFG_REG_REFCLK_PERIOD 0x2EF
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/* CONFIG_REG_8 */
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#define CFG_REG_8_OFFSET 0x2C
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#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
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#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
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/* CONFIG_REG_3/4 */
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#define CFG_REG_3_OFFSET 0x18
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#define CFG_REG_4_OFFSET 0x1C
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#define CFG_REG_DLY_CNT_SHIFT 16
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#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16)
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#define CFG_REG_REF_CNT_SHIFT 0
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#define CFG_REG_REF_CNT_MASK (0xFFFF << 0)
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/* CTRL_CORE_SMA_SW_0 */
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#define CTRL_ISOLATE_SHIFT 2
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#define CTRL_ISOLATE_MASK (1 << 2)
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#define ISOLATE_IO 1
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#define DEISOLATE_IO 0
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/* CTRL_CORE_SMA_SW_1 */
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#define RGMII2_ID_MODE_N_MASK (1 << 26)
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#define RGMII1_ID_MODE_N_MASK (1 << 25)
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/* PRM_IO_PMCTRL */
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#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0
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#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0)
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#define PMCTRL_ISOCLK_STATUS_SHIFT 1
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#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1)
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#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1
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#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0
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#define ERR_CALIBRATE_IODELAY 0x1
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#define ERR_DEISOLATE_IO 0x2
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#define ERR_ISOLATE_IO 0x4
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#define ERR_UPDATE_DELAY 0x8
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#define ERR_CPDE 0x3
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#define ERR_FPDE 0x5
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/* CFG_XXX */
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#define CFG_X_SIGNATURE_SHIFT 12
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#define CFG_X_SIGNATURE_MASK (0x3F << 12)
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#define CFG_X_LOCK_SHIFT 10
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#define CFG_X_LOCK_MASK (0x1 << 10)
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#define CFG_X_COARSE_DLY_SHIFT 5
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#define CFG_X_COARSE_DLY_MASK (0x1F << 5)
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#define CFG_X_FINE_DLY_SHIFT 0
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#define CFG_X_FINE_DLY_MASK (0x1F << 0)
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#define CFG_X_SIGNATURE 0x29
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#define CFG_X_LOCK 1
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays);
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#endif
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