mirror of
https://github.com/brain-hackers/u-boot-brain
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1d7993d1d0
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
83 lines
1.7 KiB
C
83 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <clk.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
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struct clk_pllv3 {
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struct clk clk;
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void __iomem *base;
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u32 div_mask;
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u32 div_shift;
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};
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#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
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static ulong clk_pllv3_get_rate(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
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return (div == 1) ? parent_rate * 22 : parent_rate * 20;
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}
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static const struct clk_ops clk_pllv3_generic_ops = {
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.get_rate = clk_pllv3_get_rate,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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{
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struct clk_pllv3 *pll;
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struct clk *clk;
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char *drv_name;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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switch (type) {
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case IMX_PLLV3_GENERIC:
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case IMX_PLLV3_USB:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3;
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break;
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default:
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kfree(pll);
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return ERR_PTR(-ENOTSUPP);
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}
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pll->base = base;
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pll->div_mask = div_mask;
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clk = &pll->clk;
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ret = clk_register(clk, drv_name, name, parent_name);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_pllv3_generic) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_generic_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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