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fed0509c92
As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
13 lines
338 B
Makefile
13 lines
338 B
Makefile
#
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# Makefile for at91 specific clk
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#
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obj-y += pmc.o sckc.o
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obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o
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obj-y += clk-system.o clk-peripheral.o
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obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
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obj-$(CONFIG_AT91_USB_CLK) += clk-usb.o
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obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
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obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o
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