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https://github.com/brain-hackers/u-boot-brain
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![Stefan Bosch](/assets/img/avatar_default.png)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-directory in arch/arm/mach-nexell. Appropriate line in Makefile removed. - clock.c: 'section(".data")' added to declaration of clk_periphs[] and core_hz. - Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig, e.g. "config ..." entries moved from other Kconfig. - timer.c: 'section(".data")' added to declaration of timestamp and lastdec. - arch/arm/mach-nexell/serial.c removed because this is for the UARTs of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are different, here the (existing) PL011-code is used. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
300 lines
7.4 KiB
C
300 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/clk.h>
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#if defined(CONFIG_ARCH_S5P4418)
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#include <asm/arch/reset.h>
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#endif
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#if (CONFIG_TIMER_SYS_TICK_CH > 3)
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#error Not support timer channel. Please use "0~3" channels.
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#endif
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/* global variables to save timer count
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*
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* Section ".data" must be used because BSS is not available before relocation,
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* in board_init_f(), respectively! I.e. global variables can not be used!
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*/
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static unsigned long timestamp __attribute__ ((section(".data")));
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static unsigned long lastdec __attribute__ ((section(".data")));
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static int timerinit __attribute__ ((section(".data")));
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/* macro to hw timer tick config */
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static long TIMER_FREQ = 1000000;
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static long TIMER_HZ = 1000000 / CONFIG_SYS_HZ;
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static long TIMER_COUNT = 0xFFFFFFFF;
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#define REG_TCFG0 (0x00)
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#define REG_TCFG1 (0x04)
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#define REG_TCON (0x08)
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#define REG_TCNTB0 (0x0C)
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#define REG_TCMPB0 (0x10)
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#define REG_TCNT0 (0x14)
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#define REG_CSTAT (0x44)
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#define TCON_BIT_AUTO (1 << 3)
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#define TCON_BIT_INVT (1 << 2)
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#define TCON_BIT_UP (1 << 1)
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#define TCON_BIT_RUN (1 << 0)
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#define TCFG0_BIT_CH(ch) ((ch) == 0 || (ch) == 1 ? 0 : 8)
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#define TCFG1_BIT_CH(ch) ((ch) * 4)
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#define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0)
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#define TINT_CH(ch) (ch)
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#define TINT_CSTAT_BIT_CH(ch) ((ch) + 5)
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#define TINT_CSTAT_MASK (0x1F)
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#define TIMER_TCNT_OFFS (0xC)
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void reset_timer_masked(void);
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unsigned long get_timer_masked(void);
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/*
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* Timer HW
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*/
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static inline void timer_clock(void __iomem *base, int ch, int mux, int scl)
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{
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u32 val = readl(base + REG_TCFG0) & ~(0xFF << TCFG0_BIT_CH(ch));
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writel(val | ((scl - 1) << TCFG0_BIT_CH(ch)), base + REG_TCFG0);
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val = readl(base + REG_TCFG1) & ~(0xF << TCFG1_BIT_CH(ch));
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writel(val | (mux << TCFG1_BIT_CH(ch)), base + REG_TCFG1);
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}
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static inline void timer_count(void __iomem *base, int ch, unsigned int cnt)
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{
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writel((cnt - 1), base + REG_TCNTB0 + (TIMER_TCNT_OFFS * ch));
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writel((cnt - 1), base + REG_TCMPB0 + (TIMER_TCNT_OFFS * ch));
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}
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static inline void timer_start(void __iomem *base, int ch)
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{
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int on = 0;
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u32 val = readl(base + REG_CSTAT) & ~(TINT_CSTAT_MASK << 5 | 0x1 << ch);
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writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch),
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base + REG_CSTAT);
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val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch));
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writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON);
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val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch));
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val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch));
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writel(val, base + REG_TCON);
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dmb();
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}
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static inline void timer_stop(void __iomem *base, int ch)
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{
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int on = 0;
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u32 val = readl(base + REG_CSTAT) & ~(TINT_CSTAT_MASK << 5 | 0x1 << ch);
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writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch),
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base + REG_CSTAT);
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val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch));
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writel(val, base + REG_TCON);
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}
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static inline unsigned long timer_read(void __iomem *base, int ch)
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{
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unsigned long ret;
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ret = TIMER_COUNT - readl(base + REG_TCNT0 + (TIMER_TCNT_OFFS * ch));
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return ret;
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}
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int timer_init(void)
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{
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struct clk *clk = NULL;
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char name[16] = "pclk";
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int ch = CONFIG_TIMER_SYS_TICK_CH;
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unsigned long rate, tclk = 0;
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unsigned long mout, thz, cmp = -1UL;
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int tcnt, tscl = 0, tmux = 0;
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int mux = 0, scl = 0;
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void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER;
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if (timerinit)
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return 0;
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/* get with PCLK */
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clk = clk_get(name);
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rate = clk_get_rate(clk);
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for (mux = 0; mux < 5; mux++) {
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mout = rate / (1 << mux), scl = mout / TIMER_FREQ,
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thz = mout / scl;
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if (!(mout % TIMER_FREQ) && 256 > scl) {
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tclk = thz, tmux = mux, tscl = scl;
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break;
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}
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if (scl > 256)
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continue;
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if (abs(thz - TIMER_FREQ) >= cmp)
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continue;
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tclk = thz, tmux = mux, tscl = scl;
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cmp = abs(thz - TIMER_FREQ);
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}
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tcnt = tclk; /* Timer Count := 1 Mhz counting */
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TIMER_FREQ = tcnt; /* Timer Count := 1 Mhz counting */
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TIMER_HZ = TIMER_FREQ / CONFIG_SYS_HZ;
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tcnt = TIMER_COUNT == 0xFFFFFFFF ? TIMER_COUNT + 1 : tcnt;
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timer_stop(base, ch);
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timer_clock(base, ch, tmux, tscl);
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timer_count(base, ch, tcnt);
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timer_start(base, ch);
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reset_timer_masked();
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timerinit = 1;
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return 0;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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unsigned long get_timer(unsigned long base)
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{
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long ret;
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unsigned long time = get_timer_masked();
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unsigned long hz = TIMER_HZ;
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ret = time / hz - base;
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return ret;
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}
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void set_timer(unsigned long t)
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{
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timestamp = (unsigned long)t;
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}
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void reset_timer_masked(void)
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{
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void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER;
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int ch = CONFIG_TIMER_SYS_TICK_CH;
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/* reset time */
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/* capure current decrementer value time */
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lastdec = timer_read(base, ch);
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/* start "advancing" time stamp from 0 */
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timestamp = 0;
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}
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unsigned long get_timer_masked(void)
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{
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void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER;
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int ch = CONFIG_TIMER_SYS_TICK_CH;
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unsigned long now = timer_read(base, ch); /* current tick value */
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if (now >= lastdec) { /* normal mode (non roll) */
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/* move stamp fordward with absolute diff ticks */
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timestamp += now - lastdec;
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} else {
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/* we have overflow of the count down timer */
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/* nts = ts + ld + (TLV - now)
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* ts=old stamp, ld=time that passed before passing through -1
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* (TLV-now) amount of time after passing though -1
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* nts = new "advancing time stamp"...
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* it could also roll and cause problems.
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*/
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timestamp += now + TIMER_COUNT - lastdec;
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}
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/* save last */
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lastdec = now;
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debug("now=%lu, last=%lu, timestamp=%lu\n", now, lastdec, timestamp);
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return (unsigned long)timestamp;
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}
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void __udelay(unsigned long usec)
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{
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unsigned long tmo, tmp;
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debug("+udelay=%ld\n", usec);
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if (!timerinit)
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timer_init();
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/* if "big" number, spread normalization to seconds */
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if (usec >= 1000) {
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/* start to normalize for usec to ticks per sec */
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tmo = usec / 1000;
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/* find number of "ticks" to wait to achieve target */
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tmo *= TIMER_FREQ;
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/* finish normalize. */
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tmo /= 1000;
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/* else small number, don't kill it prior to HZ multiply */
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} else {
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tmo = usec * TIMER_FREQ;
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tmo /= (1000 * 1000);
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}
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tmp = get_timer_masked(); /* get current timestamp */
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debug("A. tmo=%ld, tmp=%ld\n", tmo, tmp);
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/* if setting this fordward will roll time stamp */
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if (tmp > (tmo + tmp + 1))
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/* reset "advancing" timestamp to 0, set lastdec value */
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reset_timer_masked();
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else
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/* set advancing stamp wake up time */
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tmo += tmp;
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debug("B. tmo=%ld, tmp=%ld\n", tmo, tmp);
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/* loop till event */
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do {
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tmp = get_timer_masked();
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} while (tmo > tmp);
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debug("-udelay=%ld\n", usec);
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}
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void udelay_masked(unsigned long usec)
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{
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unsigned long tmo, endtime;
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signed long diff;
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/* if "big" number, spread normalization to seconds */
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if (usec >= 1000) {
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/* start to normalize for usec to ticks per sec */
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tmo = usec / 1000;
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/* find number of "ticks" to wait to achieve target */
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tmo *= TIMER_FREQ;
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/* finish normalize. */
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tmo /= 1000;
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} else { /* else small number, don't kill it prior to HZ multiply */
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tmo = usec * TIMER_FREQ;
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tmo /= (1000 * 1000);
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}
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endtime = get_timer_masked() + tmo;
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do {
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unsigned long now = get_timer_masked();
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diff = endtime - now;
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} while (diff >= 0);
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}
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unsigned long long get_ticks(void)
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{
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return get_timer_masked();
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}
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#if defined(CONFIG_ARCH_S5P4418)
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ulong get_tbclk(void)
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{
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ulong tbclk = TIMER_FREQ;
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return tbclk;
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}
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#endif
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