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https://github.com/brain-hackers/u-boot-brain
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c33efafaf9
The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2018, Anup Patel <anup@brainfault.org>
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* Copyright (C) 2012 Regents of the University of California
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*
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* RISC-V architecturally-defined generic timer driver
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*
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* This driver provides generic timer support for S-mode U-Boot.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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#include <asm/csr.h>
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static int riscv_timer_get_count(struct udevice *dev, u64 *count)
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{
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if (IS_ENABLED(CONFIG_64BIT)) {
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*count = csr_read(CSR_TIME);
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} else {
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u32 hi, lo;
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do {
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hi = csr_read(CSR_TIMEH);
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lo = csr_read(CSR_TIME);
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} while (hi != csr_read(CSR_TIMEH));
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*count = ((u64)hi << 32) | lo;
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}
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return 0;
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}
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static int riscv_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* clock frequency was passed from the cpu driver as driver data */
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uc_priv->clock_rate = dev->driver_data;
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return 0;
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}
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static const struct timer_ops riscv_timer_ops = {
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.get_count = riscv_timer_get_count,
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};
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U_BOOT_DRIVER(riscv_timer) = {
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.name = "riscv_timer",
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.id = UCLASS_TIMER,
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.probe = riscv_timer_probe,
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.ops = &riscv_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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