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https://github.com/brain-hackers/u-boot-brain
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fa6539a3dc
RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have specific Rx/Tx interface timings requirement for proper PHY operations. These timing values are not documented anywhere and picked from vendor code. This commits lets proper packets to be transmitted over the network. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
465 lines
12 KiB
C
465 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* RealTek PHY drivers
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*
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* Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
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* author Andy Fleming
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* Copyright 2016 Karsten Merker <merker@debian.org>
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <phy.h>
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#include <linux/delay.h>
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#define PHY_RTL8211x_FORCE_MASTER BIT(1)
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#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
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#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
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#define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000
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/* RTL8211x 1000BASE-T Control Register */
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#define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
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#define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
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/* RTL8211x PHY Status Register */
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#define MIIM_RTL8211x_PHY_STATUS 0x11
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#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
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#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
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#define MIIM_RTL8211x_PHYSTAT_100 0x4000
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#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
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#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
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#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
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/* RTL8211x PHY Interrupt Enable Register */
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#define MIIM_RTL8211x_PHY_INER 0x12
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#define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
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#define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
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/* RTL8211x PHY Interrupt Status Register */
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#define MIIM_RTL8211x_PHY_INSR 0x13
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/* RTL8211F PHY Status Register */
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#define MIIM_RTL8211F_PHY_STATUS 0x1a
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#define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
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#define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
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#define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
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#define MIIM_RTL8211F_PHYSTAT_100 0x0010
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#define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
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#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
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#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
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#define MIIM_RTL8211E_CONFREG 0x1c
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#define MIIM_RTL8211E_CONFREG_TXD 0x0002
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#define MIIM_RTL8211E_CONFREG_RXD 0x0004
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#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
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#define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
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#define MIIM_RTL8211F_PAGE_SELECT 0x1f
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#define MIIM_RTL8211F_TX_DELAY 0x100
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#define MIIM_RTL8211F_RX_DELAY 0x8
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#define MIIM_RTL8211F_LCR 0x10
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#define RTL8201F_RMSR 0x10
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#define RMSR_RX_TIMING_SHIFT BIT(2)
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#define RMSR_RX_TIMING_MASK GENMASK(7, 4)
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#define RMSR_RX_TIMING_VAL 0x4
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#define RMSR_TX_TIMING_SHIFT BIT(3)
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#define RMSR_TX_TIMING_MASK GENMASK(11, 8)
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#define RMSR_TX_TIMING_VAL 0x5
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static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
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int devaddr, int regnum)
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{
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int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT);
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int val;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
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val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
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return val;
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}
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static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
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phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
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return 0;
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}
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static int rtl8211b_probe(struct phy_device *phydev)
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{
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#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
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phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
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#endif
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return 0;
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}
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static int rtl8211e_probe(struct phy_device *phydev)
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{
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#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
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phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
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#endif
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return 0;
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}
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static int rtl8211f_probe(struct phy_device *phydev)
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{
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#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
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phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
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#endif
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return 0;
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}
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static int rtl8210f_probe(struct phy_device *phydev)
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{
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#ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS
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phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS;
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#endif
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return 0;
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}
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/* RealTek RTL8211x */
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static int rtl8211x_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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/* mask interrupt at init; if the interrupt is
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* needed indeed, it should be explicitly enabled
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
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MIIM_RTL8211x_PHY_INTR_DIS);
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if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
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unsigned int reg;
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
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/* force manual master/slave configuration */
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reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
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/* force master mode */
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reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
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}
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if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
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unsigned int reg;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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7);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
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/* Ensure both internal delays are turned off */
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reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
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/* Flip the magic undocumented bits */
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reg |= MIIM_RTL8211E_CONFREG_MAGIC;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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0);
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}
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/* read interrupt status just to clear it */
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phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
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genphy_config_aneg(phydev);
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return 0;
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}
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/* RealTek RTL8201F */
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static int rtl8201f_config(struct phy_device *phydev)
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{
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unsigned int reg;
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if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) {
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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7);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);
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reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);
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/* Set the needed Rx/Tx Timings for proper PHY operation */
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reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)
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| (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);
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phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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0);
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}
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genphy_config_aneg(phydev);
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return 0;
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}
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static int rtl8211f_config(struct phy_device *phydev)
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{
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u16 reg;
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if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
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unsigned int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
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reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
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phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
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}
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT, 0xd08);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
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/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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reg |= MIIM_RTL8211F_TX_DELAY;
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else
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reg &= ~MIIM_RTL8211F_TX_DELAY;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
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/* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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reg |= MIIM_RTL8211F_RX_DELAY;
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else
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reg &= ~MIIM_RTL8211F_RX_DELAY;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
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/* restore to default page 0 */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT, 0x0);
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/* Set green LED for Link, yellow LED for Active */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT, 0xd04);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PAGE_SELECT, 0x0);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int rtl8211x_parse_status(struct phy_device *phydev)
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{
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unsigned int speed;
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unsigned int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
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if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
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int i = 0;
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/* in case of timeout ->link is cleared */
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phydev->link = 1;
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puts("Waiting for PHY realtime link");
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while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
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/* Timeout reached ? */
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phydev->link = 0;
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break;
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}
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if ((i++ % 1000) == 0)
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putc('.');
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udelay(1000); /* 1 ms */
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211x_PHY_STATUS);
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}
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puts(" done\n");
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udelay(500000); /* another 500 ms (results in faster booting) */
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} else {
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if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
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phydev->link = 1;
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else
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phydev->link = 0;
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}
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if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
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switch (speed) {
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case MIIM_RTL8211x_PHYSTAT_GBIT:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_RTL8211x_PHYSTAT_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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}
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return 0;
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}
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static int rtl8211f_parse_status(struct phy_device *phydev)
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{
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unsigned int speed;
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unsigned int mii_reg;
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int i = 0;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
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phydev->link = 1;
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while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phydev->link = 0;
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break;
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}
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if ((i++ % 1000) == 0)
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putc('.');
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udelay(1000);
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211F_PHY_STATUS);
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}
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if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
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switch (speed) {
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case MIIM_RTL8211F_PHYSTAT_GBIT:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_RTL8211F_PHYSTAT_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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}
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return 0;
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}
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static int rtl8211x_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return rtl8211x_parse_status(phydev);
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}
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static int rtl8211e_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return genphy_parse_link(phydev);
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}
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static int rtl8211f_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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/* Read the Status (2x to make sure link is right) */
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return rtl8211f_parse_status(phydev);
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}
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/* Support for RTL8211B PHY */
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static struct phy_driver RTL8211B_driver = {
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.name = "RealTek RTL8211B",
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.uid = 0x1cc912,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.probe = &rtl8211b_probe,
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.config = &rtl8211x_config,
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.startup = &rtl8211x_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
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static struct phy_driver RTL8211E_driver = {
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.name = "RealTek RTL8211E",
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.uid = 0x1cc915,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.probe = &rtl8211e_probe,
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.config = &rtl8211x_config,
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.startup = &rtl8211e_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Support for RTL8211DN PHY */
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static struct phy_driver RTL8211DN_driver = {
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.name = "RealTek RTL8211DN",
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.uid = 0x1cc914,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211x_config,
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.startup = &rtl8211x_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Support for RTL8211F PHY */
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static struct phy_driver RTL8211F_driver = {
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.name = "RealTek RTL8211F",
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.uid = 0x1cc916,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.probe = &rtl8211f_probe,
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.config = &rtl8211f_config,
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.startup = &rtl8211f_startup,
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.shutdown = &genphy_shutdown,
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.readext = &rtl8211f_phy_extread,
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.writeext = &rtl8211f_phy_extwrite,
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};
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/* Support for RTL8201F PHY */
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static struct phy_driver RTL8201F_driver = {
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.name = "RealTek RTL8201F 10/100Mbps Ethernet",
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.uid = 0x1cc816,
|
|
.mask = 0xffffff,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.probe = &rtl8210f_probe,
|
|
.config = &rtl8201f_config,
|
|
.startup = &rtl8211e_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
int phy_realtek_init(void)
|
|
{
|
|
phy_register(&RTL8211B_driver);
|
|
phy_register(&RTL8211E_driver);
|
|
phy_register(&RTL8211F_driver);
|
|
phy_register(&RTL8211DN_driver);
|
|
phy_register(&RTL8201F_driver);
|
|
|
|
return 0;
|
|
}
|