mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 04:48:52 +09:00
![]() In all reference designs the FCLK1 runs at 150MHz, but the bootloader doesn't set it up like that. Set the divider to 8 to generate the correct clock. Fixes (a.o.) the DMA speed being too slow. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
||
---|---|---|
.. | ||
zynq |