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![]() The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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eth.c | ||
Kconfig | ||
ls1012aqds_pfe.h | ||
ls1012aqds_qixis.h | ||
ls1012aqds.c | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LS1012A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A SoC overview. LS1012AQDS board Overview ----------------------- - SERDES Connections, 4 lanes supporting: - PCI Express - 3.0 - SGMII, SGMII 2.5 - SATA 3.0 - DDR Controller - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s - QSPI Controller - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select signals to QSPI NOR flash memory (2 virtual banks) and the QSPI emulator - USB 3.0 - One USB 3.0 controller with integrated PHY - One high-speed USB 3.0 port - USB 2.0 - One USB 2.0 controller with ULPI interface - Two enhanced secure digital host controllers: - SDHC1 controller can be connected to onboard SDHC connector - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices - 2 I2C controllers - One SATA onboard connectors - UART - 5 SAI - One SAI port with audio codec SGTL5000: • Provides MIC bias • Provides headphone and line output - One SAI port terminated at 2x6 header - Three SAI Tx/Rx ports terminated at 2x3 headers - ARM JTAG support Booting Options --------------- a) QSPI Flash Emu Boot b) QSPI Flash 1 c) QSPI Flash 2 QSPI flash map -------------- Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 U-boot | 1MB | 0x4010_0000 U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000