mirror of
https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
701 lines
18 KiB
C
701 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#include <command.h>
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#include <image.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <bmp_logo.h>
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#include <dm/root.h>
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#include <env.h>
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#include <i2c_eeprom.h>
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#include <i2c.h>
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#include <micrel.h>
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#include <miiphy.h>
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#include <lcd.h>
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#include <led.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <power/da9063_pmic.h>
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#include <splash.h>
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#include <video_fb.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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BOARD_TYPE_4 = 4,
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BOARD_TYPE_7 = 7,
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};
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#define ARI_BT_4 "aristainetos2_4@2"
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#define ARI_BT_7 "aristainetos2_7@1"
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int board_phy_config(struct phy_device *phydev)
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{
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/* control data pad skew - devaddr = 0x02, register = 0x04 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* rx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* tx data pad skew - devaddr = 0x02, register = 0x06 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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static int rotate_logo_one(unsigned char *out, unsigned char *in)
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{
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int i, j;
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for (i = 0; i < BMP_LOGO_WIDTH; i++)
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for (j = 0; j < BMP_LOGO_HEIGHT; j++)
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out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
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in[i * BMP_LOGO_WIDTH + j];
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return 0;
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}
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/*
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* Rotate the BMP_LOGO (only)
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* Will only work, if the logo is square, as
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* BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
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*/
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void rotate_logo(int rotations)
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{
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unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
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struct bmp_header *header;
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unsigned char *in_logo;
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int i, j;
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if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
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return;
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header = (struct bmp_header *)bmp_logo_bitmap;
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in_logo = bmp_logo_bitmap + header->data_offset;
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/* one 90 degree rotation */
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if (rotations == 1 || rotations == 2 || rotations == 3)
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rotate_logo_one(out_logo, in_logo);
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/* second 90 degree rotation */
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if (rotations == 2 || rotations == 3)
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rotate_logo_one(in_logo, out_logo);
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/* third 90 degree rotation */
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if (rotations == 3)
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rotate_logo_one(out_logo, in_logo);
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/* copy result back to original array */
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if (rotations == 1 || rotations == 3)
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for (i = 0; i < BMP_LOGO_WIDTH; i++)
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for (j = 0; j < BMP_LOGO_HEIGHT; j++)
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in_logo[i * BMP_LOGO_WIDTH + j] =
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out_logo[i * BMP_LOGO_WIDTH + j];
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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/* set PLL5 clock */
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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/* set PLL5 to 232720000Hz */
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
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reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
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writel(reg, &ccm->analog_pll_video);
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
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&ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
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&ccm->analog_pll_video_denom);
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reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
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reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
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writel(reg, &ccm->analog_pll_video);
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/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
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reg = readl(&ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
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| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &ccm->cs2cdr);
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reg = readl(&ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &ccm->cscmr2);
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reg = readl(&ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
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| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
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| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
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| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
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| IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
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| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
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| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
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<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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static void enable_spi_display(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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#if defined(CONFIG_VIDEO_BMP_LOGO)
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rotate_logo(3); /* portrait display in landscape mode */
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#endif
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reg = readl(&ccm->cs2cdr);
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/* select pll 5 clock */
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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writel(reg, &ccm->cs2cdr);
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/* set PLL5 to 197994996Hz */
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
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reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
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writel(reg, &ccm->analog_pll_video);
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
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&ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
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&ccm->analog_pll_video_denom);
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reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
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reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
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writel(reg, &ccm->analog_pll_video);
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/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
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reg = readl(&ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
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| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &ccm->cs2cdr);
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reg = readl(&ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &ccm->cscmr2);
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reg = readl(&ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
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reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
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reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
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reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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writel(reg, &ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
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| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
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| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
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| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
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| IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
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| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
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| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
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<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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static void setup_display(void)
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{
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enable_ipu_clock();
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}
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static void set_gpr_register(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
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IOMUXC_GPR1_EXC_MON_SLVE |
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(2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
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IOMUXC_GPR1_ACT_CS0,
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&iomuxc_regs->gpr[1]);
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writel(0x0, &iomuxc_regs->gpr[8]);
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writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
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IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
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&iomuxc_regs->gpr[12]);
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}
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extern char __bss_start[], __bss_end[];
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int board_early_init_f(void)
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{
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select_ldb_di_clock_source(MXC_PLL5_CLK);
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set_gpr_register();
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/*
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* clear bss here, so we can use spi driver
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* before relocation and read Environment
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* from spi flash.
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*/
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memset(__bss_start, 0x00, __bss_end - __bss_start);
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return 0;
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}
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static void setup_one_led(char *label, int state)
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{
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struct udevice *dev;
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int ret;
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ret = led_get_by_label(label, &dev);
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if (ret == 0)
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led_set_state(dev, state);
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}
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static void setup_board_gpio(void)
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{
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setup_one_led("led_ena", LEDST_ON);
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/* switch off Status LEDs */
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setup_one_led("led_yellow", LEDST_OFF);
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setup_one_led("led_red", LEDST_OFF);
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setup_one_led("led_green", LEDST_OFF);
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setup_one_led("led_blue", LEDST_OFF);
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}
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#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
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" rescueReason=%d "
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static void aristainetos_run_rescue_command(int reason)
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{
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char rescue_reason_command[80];
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sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
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run_command(rescue_reason_command, 0);
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}
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static int aristainetos_eeprom(void)
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{
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struct udevice *dev;
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int off;
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int ret;
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u8 data[0x10];
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u8 rescue_reason;
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off = fdt_path_offset(gd->fdt_blob, "eeprom0");
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if (off < 0) {
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printf("%s: No eeprom0 path offset\n", __func__);
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return off;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
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if (ret) {
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printf("%s: Could not find EEPROM\n", __func__);
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return ret;
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}
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ret = i2c_set_chip_offset_len(dev, 2);
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if (ret)
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return ret;
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ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
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if (ret) {
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printf("%s: Could not read EEPROM\n", __func__);
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return ret;
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}
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if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
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rescue_reason = *(uint8_t *)&data[9];
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memset(&data[3], 0xff, 7);
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i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
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printf("\nBooting into Rescue System (EEPROM)\n");
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aristainetos_run_rescue_command(rescue_reason);
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run_command("run rescue_load_fit rescueboot", 0);
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} else if (strncmp((char *)data, "DeF", 3) == 0) {
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memset(data, 0xff, 3);
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i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
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printf("\nClear u-boot environment (set back to defaults)\n");
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run_command("run default_env; saveenv; saveenv", 0);
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}
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return 0;
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};
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static void aristainetos_bootmode_settings(void)
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{
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struct gpio_desc *desc;
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned int sbmr1 = readl(&psrc->sbmr1);
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char *my_bootdelay;
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char bootmode = 0;
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int ret;
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/*
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* Check the boot-source. If booting from NOR Flash,
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* disable bootdelay
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*/
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ret = gpio_hog_lookup_name("bootsel0", &desc);
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if (!ret)
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bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
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ret = gpio_hog_lookup_name("bootsel1", &desc);
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if (!ret)
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bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
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ret = gpio_hog_lookup_name("bootsel2", &desc);
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if (!ret)
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bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
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if (bootmode == 7) {
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my_bootdelay = env_get("nor_bootdelay");
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if (my_bootdelay)
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env_set("bootdelay", my_bootdelay);
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else
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env_set("bootdelay", "-2");
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}
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if (sbmr1 & 0x40) {
|
|
env_set("bootmode", "1");
|
|
printf("SD bootmode jumper set!\n");
|
|
} else {
|
|
env_set("bootmode", "0");
|
|
}
|
|
|
|
/* read out some jumper values*/
|
|
ret = gpio_hog_lookup_name("env_reset", &desc);
|
|
if (!ret) {
|
|
if (dm_gpio_get_value(desc)) {
|
|
printf("\nClear env (set back to defaults)\n");
|
|
run_command("run default_env; saveenv; saveenv", 0);
|
|
}
|
|
}
|
|
ret = gpio_hog_lookup_name("boot_rescue", &desc);
|
|
if (!ret) {
|
|
if (dm_gpio_get_value(desc)) {
|
|
aristainetos_run_rescue_command(16);
|
|
run_command("run rescue_xload_boot", 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_DM_PMIC_DA9063)
|
|
/*
|
|
* On the aristainetos2c boards the PMIC needs to be initialized,
|
|
* because the Ethernet PHY uses a different regulator that is not
|
|
* setup per hardware default. This does not influence the other versions
|
|
* as this regulator isn't used there at all.
|
|
*
|
|
* Unfortunately we have not yet a interface to setup all
|
|
* values we need.
|
|
*/
|
|
static int setup_pmic_voltages(void)
|
|
{
|
|
struct udevice *dev;
|
|
int off;
|
|
int ret;
|
|
|
|
off = fdt_path_offset(gd->fdt_blob, "pmic0");
|
|
if (off < 0) {
|
|
printf("%s: No pmic path offset\n", __func__);
|
|
return off;
|
|
}
|
|
|
|
ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
|
|
if (ret) {
|
|
printf("%s: Could not find PMIC\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
|
|
pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
|
|
ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
|
|
if (ret < 0) {
|
|
printf("%s: error %d get register\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
ret &= 0xf0;
|
|
ret |= 0x09;
|
|
pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
|
|
pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
|
|
pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int setup_pmic_voltages(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
int x, y;
|
|
|
|
led_default_state();
|
|
splash_get_pos(&x, &y);
|
|
bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
|
|
|
|
aristainetos_bootmode_settings();
|
|
|
|
/* eeprom work */
|
|
aristainetos_eeprom();
|
|
|
|
/* set board_type */
|
|
if (gd->board_type == BOARD_TYPE_4)
|
|
env_set("board_type", ARI_BT_4);
|
|
else
|
|
env_set("board_type", ARI_BT_7);
|
|
|
|
if (setup_pmic_voltages())
|
|
printf("Error setup PMIC\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = imx_ddr_size();
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct display_info_t const displays[] = {
|
|
{
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = NULL,
|
|
.enable = enable_lvds,
|
|
.mode = {
|
|
.name = "lb07wv8",
|
|
.refresh = 60,
|
|
.xres = 800,
|
|
.yres = 480,
|
|
.pixclock = 30066,
|
|
.left_margin = 88,
|
|
.right_margin = 88,
|
|
.upper_margin = 20,
|
|
.lower_margin = 20,
|
|
.hsync_len = 80,
|
|
.vsync_len = 5,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
}
|
|
}
|
|
#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
|
|
(CONFIG_SYS_BOARD_VERSION == 3) || \
|
|
(CONFIG_SYS_BOARD_VERSION == 4) || \
|
|
(CONFIG_SYS_BOARD_VERSION == 5))
|
|
, {
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = NULL,
|
|
.enable = enable_spi_display,
|
|
.mode = {
|
|
.name = "lg4573",
|
|
.refresh = 57,
|
|
.xres = 480,
|
|
.yres = 800,
|
|
.pixclock = 37037,
|
|
.left_margin = 59,
|
|
.right_margin = 10,
|
|
.upper_margin = 15,
|
|
.lower_margin = 15,
|
|
.hsync_len = 10,
|
|
.vsync_len = 15,
|
|
.sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
|
|
FB_SYNC_VERT_HIGH_ACT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
}
|
|
}
|
|
#endif
|
|
};
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
|
|
#if defined(CONFIG_MTD_RAW_NAND)
|
|
iomux_v3_cfg_t nfc_pads[] = {
|
|
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_gpmi_nand(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* config gpmi nand iomux */
|
|
imx_iomux_v3_setup_multiple_pads(nfc_pads,
|
|
ARRAY_SIZE(nfc_pads));
|
|
|
|
/* gate ENFC_CLK_ROOT clock first,before clk source switch */
|
|
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
|
|
|
/* config gpmi and bch clock to 100 MHz */
|
|
clrsetbits_le32(&mxc_ccm->cs2cdr,
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
|
|
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
|
|
|
|
/* enable ENFC_CLK_ROOT clock */
|
|
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
|
|
|
/* enable gpmi and bch clock gating */
|
|
setbits_le32(&mxc_ccm->CCGR4,
|
|
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
|
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
|
|
|
|
/* enable apbh clock gating */
|
|
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
|
}
|
|
#else
|
|
static void setup_gpmi_nand(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
setup_board_gpio();
|
|
setup_gpmi_nand();
|
|
setup_display();
|
|
|
|
/* GPIO_1 for USB_OTG_ID */
|
|
clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
|
|
return 0;
|
|
}
|
|
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
if (gd->board_type == BOARD_TYPE_4 &&
|
|
strchr(name, 0x34))
|
|
return 0;
|
|
|
|
if (gd->board_type == BOARD_TYPE_7 &&
|
|
strchr(name, 0x37))
|
|
return 0;
|
|
|
|
return -1;
|
|
}
|
|
|
|
static void do_board_detect(void)
|
|
{
|
|
int ret;
|
|
char s[30];
|
|
|
|
/* default use board type 7 */
|
|
gd->board_type = BOARD_TYPE_7;
|
|
if (env_init())
|
|
return;
|
|
|
|
ret = env_get_f("panel", s, sizeof(s));
|
|
if (ret < 0)
|
|
return;
|
|
|
|
if (!strncmp("lg4573", s, 6))
|
|
gd->board_type = BOARD_TYPE_4;
|
|
}
|
|
|
|
#ifdef CONFIG_DTB_RESELECT
|
|
int embedded_dtb_select(void)
|
|
{
|
|
int rescan;
|
|
|
|
do_board_detect();
|
|
fdtdec_resetup(&rescan);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|