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https://github.com/brain-hackers/u-boot-brain
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81e33f4b65
Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
43 lines
930 B
C
43 lines
930 B
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define TIMER_LOAD_VAL 0xffffffff
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static int init_done __attribute__((section(".data"))) = 0;
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/*
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* Timer initialization
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*/
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int timer_init(void)
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{
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/* Only init the timer once */
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if (init_done)
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return 0;
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init_done = 1;
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/* load value into timer */
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writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
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writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
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#if defined(CONFIG_ARCH_MVEBU)
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/* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
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setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
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#endif
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/* enable timer in auto reload mode */
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setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3);
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return 0;
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}
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