mirror of
https://github.com/brain-hackers/u-boot-brain
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77b55e8cfc
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
59 lines
1.1 KiB
C
59 lines
1.1 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TZPC_H_
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#define __TZPC_H_
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#ifndef __ASSEMBLY__
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struct exynos_tzpc {
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unsigned int r0size;
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char res1[0x7FC];
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unsigned int decprot0stat;
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unsigned int decprot0set;
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unsigned int decprot0clr;
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unsigned int decprot1stat;
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unsigned int decprot1set;
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unsigned int decprot1clr;
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unsigned int decprot2stat;
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unsigned int decprot2set;
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unsigned int decprot2clr;
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unsigned int decprot3stat;
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unsigned int decprot3set;
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unsigned int decprot3clr;
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char res2[0x7B0];
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unsigned int periphid0;
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unsigned int periphid1;
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unsigned int periphid2;
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unsigned int periphid3;
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unsigned int pcellid0;
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unsigned int pcellid1;
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unsigned int pcellid2;
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unsigned int pcellid3;
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};
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#define EXYNOS4_NR_TZPC_BANKS 6
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#define EXYNOS5_NR_TZPC_BANKS 10
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/* TZPC : Register Offsets */
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#define TZPC_BASE_OFFSET 0x10000
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/*
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* TZPC Register Value :
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* R0SIZE: 0x0 : Size of secured ram
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*/
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#define R0SIZE 0x0
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/*
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* TZPC Decode Protection Register Value :
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* DECPROTXSET: 0xFF : Set Decode region to non-secure
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*/
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#define DECPROTXSET 0xFF
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void tzpc_init(void);
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#endif
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#endif
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