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https://github.com/brain-hackers/u-boot-brain
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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
141 lines
3.2 KiB
C
141 lines
3.2 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pit.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/io.h>
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#include <div64.h>
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/*
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* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
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* setting the 20 bit counter period to its maximum (0xfffff).
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*/
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#define TIMER_LOAD_VAL 0xfffff
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#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
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#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
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static ulong timestamp;
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static ulong lastinc;
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static ulong timer_freq;
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, timer_freq);
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return tick;
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}
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static inline unsigned long long usec_to_tick(unsigned long long usec)
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{
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usec *= timer_freq;
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do_div(usec, 1000000);
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return usec;
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}
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/* nothing really to do with interrupts, just starts up a counter. */
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int timer_init(void)
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{
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/*
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* Enable PITC Clock
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* The clock is already enabled for system controller in boot
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*/
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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/* Enable PITC */
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at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
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reset_timer_masked();
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timer_freq = get_mck_clk_rate() >> 4;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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unsigned long long get_ticks(void)
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{
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ulong now = READ_TIMER;
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp forward with absolut diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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void reset_timer_masked(void)
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{
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/* reset time */
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lastinc = READ_TIMER; /* capture current incrementer value time */
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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ulong get_timer_masked(void)
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{
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return tick_to_time(get_ticks());
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}
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void __udelay(unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = usec_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked () - base;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CONFIG_SYS_HZ;
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return tbclk;
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}
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