mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 13:23:44 +09:00
7f52ed5ef1
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __BCSR_H_
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#define __BCSR_H_
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#include <common.h>
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/* BCSR Bit definitions*/
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/****************************************/
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/* BCSR defines */
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/****************************************/
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#define BCSR6_UPC1_EN 0x80
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#define BCSR6_UPC1_POS_EN 0x40
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#define BCSR6_UPC1_ADDR_EN 0x20
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#define BCSR6_UPC1_DEV2 0x10
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#define BCSR6_SD_CARD_1BIT 0x08
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#define BCSR6_SD_CARD_4BITS 0x04
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#define BCSR6_TDM2G_EN 0x02
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#define BCSR6_UCC7_RMII_EN 0x01
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#define BCSR7_UCC1_GETH_EN 0x80
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#define BCSR7_UCC1_RGMII_EN 0x40
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#define BCSR7_UCC1_RTBI_EN 0x20
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#define BCSR7_GETHRST_MRVL 0x04
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#define BCSR7_BRD_WRT_PROTECT 0x02
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#define BCSR8_UCC2_GETH_EN 0x80
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#define BCSR8_UCC2_RGMII_EN 0x40
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#define BCSR8_UCC2_RTBI_EN 0x20
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#define BCSR8_UEM_MARVEL_RESET 0x02
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#define BCSR9_UCC3_GETH_EN 0x80
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#define BCSR9_UCC3_RGMII_EN 0x40
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#define BCSR9_UCC3_RTBI_EN 0x20
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#define BCSR9_UCC3_RMII_EN 0x10
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#define BCSR9_UCC3_UEM_MICREL 0x01
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#define BCSR10_UCC4_GETH_EN 0x80
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#define BCSR10_UCC4_RGMII_EN 0x40
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#define BCSR10_UCC4_RTBI_EN 0x20
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#define BCSR11_LED0 0x40
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#define BCSR11_LED1 0x20
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#define BCSR11_LED2 0x10
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#define BCSR12_UCC6_RMII_EN 0x20
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#define BCSR12_UCC8_RMII_EN 0x20
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#define BCSR15_SMII6_DIS 0x08
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#define BCSR15_SMII8_DIS 0x04
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#define BCSR16_UPC1_DEV2 0x02
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#define BCSR17_FLASH_nWP 0x01
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/*BCSR Utils functions*/
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void enable_8569mds_flash_write(void);
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void disable_8569mds_flash_write(void);
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void enable_8569mds_qe_uec(void);
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void disable_8569mds_brd_eeprom_write_protect(void);
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#endif /* __BCSR_H_ */
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