mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
b186cfa1a3
Pass rtc_status via the device tree, instead of on kernel command line. Additionally, the 2038 mitigation is reported, if applied successfully. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
222 lines
6.4 KiB
C
222 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Timesys Corporation
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* Copyright (C) 2015 General Electric Company
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* Copyright (C) 2014 Advantech
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the GE MX6Q Bx50v3 boards.
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*/
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#ifndef __GE_BX50V3_CONFIG_H
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#define __GE_BX50V3_CONFIG_H
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#include <asm/arch/imx-regs.h>
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#include <asm/mach-imx/gpio.h>
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#define CONFIG_BOARD_NAME "General Electric Bx50v3"
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#define CONFIG_MXC_UART_BASE UART3_BASE
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#define CONSOLE_DEV "ttymxc2"
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#include "mx6_common.h"
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#include <linux/sizes.h>
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
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#define CONFIG_MXC_UART
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/* SATA Configs */
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#ifdef CONFIG_CMD_SATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 1
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#define CONFIG_DWC_AHSATA_PORT_ID 0
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#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
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#define CONFIG_LBA48
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#endif
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/* USB Configs */
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#ifdef CONFIG_USB
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USBD_HS
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#define CONFIG_USB_GADGET_MASS_STORAGE
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#endif
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/* Serial Flash */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_LOADADDR 0x12000000
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#ifdef CONFIG_NFS_CMD
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#define NETWORKBOOT \
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"setnetworkboot=" \
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"setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \
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"setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \
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"setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \
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"setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \
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"setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \
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"setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \
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"setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \
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"setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \
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"networkboot=" \
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"run setnetworkboot; " \
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"nfs ${loadaddr} /srv/nfs/fitImage; " \
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"bootm ${loadaddr}#conf@${confidx}\0" \
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#define CONFIG_NETWORKBOOTCOMMAND \
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"run networkboot; " \
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#else
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#define NETWORKBOOT \
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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NETWORKBOOT \
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"bootcause=POR\0" \
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"image=/boot/fitImage\0" \
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"fdt_high=0xffffffff\0" \
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"dev=mmc\0" \
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"devnum=2\0" \
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"rootdev=mmcblk0p\0" \
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"quiet=quiet loglevel=0\0" \
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"console=" CONSOLE_DEV "\0" \
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"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
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"ro rootwait cma=128M " \
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"bootcause=${bootcause} " \
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"${quiet} console=${console} " \
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"${videoargs}" "\0" \
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"doquiet=" \
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"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
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"then setenv quiet; fi\0" \
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"hasfirstboot=" \
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"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
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"/boot/bootcause/firstboot\0" \
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"swappartitions=" \
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"setexpr partnum 3 - ${partnum}\0" \
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"failbootcmd=" \
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"echo reached failbootcmd; " \
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"bx50_backlight_enable; " \
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"setcurs 5 4; " \
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"lcdputs \"Monitor failed to start. " \
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"Try again, or contact GE Service for support.\"; " \
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"mw.b 0x7000A000 0xbc; " \
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"mw.b 0x7000A001 0x00; " \
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"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
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"altbootcmd=" \
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"run doquiet; " \
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"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
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"run hasfirstboot || setenv partnum 0; " \
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"if test ${partnum} != 0; then " \
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"setenv bootcause REVERT; " \
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"run swappartitions loadimage doboot; " \
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"fi; " \
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"run failbootcmd\0" \
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"loadimage=" \
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"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
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"doboot=" \
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"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
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"run setargs; " \
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"bootm ${loadaddr}#conf@${confidx}\0" \
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"tryboot=" \
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"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
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"run loadimage || run swappartitions && run loadimage || " \
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"setenv partnum 0 && echo MISSING IMAGE;" \
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"run doboot; " \
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"run failbootcmd\0" \
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#define CONFIG_MMCBOOTCOMMAND \
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"if mmc dev ${devnum}; then " \
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"run doquiet; " \
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"run tryboot; " \
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"fi; " \
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#define CONFIG_USBBOOTCOMMAND \
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"echo Unsupported; " \
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#ifdef CONFIG_NFS_CMD
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#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
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#elif CONFIG_CMD_USB
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#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
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#else
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#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_MEMTEST_START 0x10000000
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#define CONFIG_SYS_MEMTEST_END 0x10010000
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* environment organization */
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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/* Framebuffer */
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#define CONFIG_HIDE_LOGO_VERSION
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#define CONFIG_CMD_BMP
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#define CONFIG_IMX6_PWM_PER_CLK 66000000
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
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#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
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#define CONFIG_RTC_RX8010SJ
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#define CONFIG_SYS_RTC_BUS_NUM 2
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#define CONFIG_SYS_I2C_RTC_ADDR 0x32
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_MXC_I2C1
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#define CONFIG_SYS_I2C_MXC_I2C2
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_NUM_I2C_BUSES 11
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
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{1, {I2C_NULL_HOP} }, \
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{2, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
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}
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#define CONFIG_BCH
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#endif /* __GE_BX50V3_CONFIG_H */
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