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https://github.com/brain-hackers/u-boot-brain
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a78cd86132
As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* Copyright (C) 2016 ARM Ltd.
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*
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* ARM and ARM64 barrier instructions
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* split from armv7.h to allow sharing between ARM and ARM64
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*
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* Original copyright in armv7.h was:
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* (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
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*
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* Much of the original barrier code was contributed by:
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* Valentine Barshak <valentine.barshak@cogentembedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __BARRIERS_H__
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#define __BARRIERS_H__
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#ifndef __ASSEMBLY__
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#ifndef CONFIG_ARM64
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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#endif /* !CONFIG_ARM64 */
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#if __LINUX_ARM_ARCH__ >= 7
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#define ISB asm volatile ("isb sy" : : : "memory")
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#define DSB asm volatile ("dsb sy" : : : "memory")
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#define DMB asm volatile ("dmb sy" : : : "memory")
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#elif __LINUX_ARM_ARCH__ == 6
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#define ISB CP15ISB
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#define DSB CP15DSB
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#define DMB CP15DMB
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#else
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#define ISB asm volatile ("" : : : "memory")
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#define DSB CP15DSB
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#define DMB asm volatile ("" : : : "memory")
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#endif
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#define isb() ISB
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#define dsb() DSB
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#define dmb() DMB
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#endif /* __ASSEMBLY__ */
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#endif /* __BARRIERS_H__ */
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