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09959ba3c5
Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/*
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* (C) Copyright 2011
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* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* Copyright 2015 ATS Advanced Telematics Systems GmbH
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* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MACH_STM32_H_
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#define _MACH_STM32_H_
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/*
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* Peripheral memory map
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*/
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#define STM32_PERIPH_BASE 0x40000000
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#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
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#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
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#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000)
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#define STM32_BUS_MASK 0xFFFF0000
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#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
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#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
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#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
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#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
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#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
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#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
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#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
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/*
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* Register maps
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*/
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struct stm32_des_regs {
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u16 flash_size;
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u16 pad1;
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u32 pad2;
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u32 uid0;
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u32 uid1;
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u32 uid2;
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};
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struct stm32_rcc_regs {
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u32 cr; /* RCC clock control */
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u32 cfgr; /* RCC clock configuration */
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u32 cir; /* RCC clock interrupt */
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u32 apb2rstr; /* RCC APB2 peripheral reset */
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u32 apb1rstr; /* RCC APB1 peripheral reset */
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u32 ahbenr; /* RCC AHB peripheral clock enable */
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u32 apb2enr; /* RCC APB2 peripheral clock enable */
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u32 apb1enr; /* RCC APB1 peripheral clock enable */
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u32 bdcr; /* RCC Backup domain control */
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u32 csr; /* RCC clock control & status */
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};
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struct stm32_pwr_regs {
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u32 cr;
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u32 csr;
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};
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struct stm32_flash_regs {
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u32 acr;
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u32 keyr;
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u32 optkeyr;
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u32 sr;
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u32 cr;
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u32 ar;
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u32 rsvd1; /* Reserved */
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u32 obr;
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u32 wrpr;
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u32 rsvd2[8]; /* Reserved */
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u32 keyr2;
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u32 rsvd3;
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u32 sr2;
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u32 cr2;
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u32 ar2;
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};
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/* Per bank register set for XL devices */
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struct stm32_flash_bank_regs {
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u32 keyr;
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u32 rsvd; /* Reserved */
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u32 sr;
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u32 cr;
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u32 ar;
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};
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/*
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* Registers access macros
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*/
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#define STM32_DES_BASE (0x1ffff7e0)
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#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE)
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#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000)
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#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
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#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
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#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
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#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000)
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#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
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#define STM32_FLASH_SR_BSY (1 << 0)
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#define STM32_FLASH_CR_PG (1 << 0)
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#define STM32_FLASH_CR_PER (1 << 1)
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#define STM32_FLASH_CR_STRT (1 << 6)
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#define STM32_FLASH_CR_LOCK (1 << 7)
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enum clock {
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CLOCK_CORE,
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CLOCK_AHB,
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CLOCK_APB1,
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CLOCK_APB2
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};
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int configure_clocks(void);
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unsigned long clock_get(enum clock clck);
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#endif /* _MACH_STM32_H_ */
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