mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 14:53:26 +09:00
ac0d98cd55
This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel. Secondary core power down happens in following steps: Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
132 lines
4.1 KiB
C
132 lines
4.1 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARM_ARCH_SYSTEM_H_
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#define __ASM_ARM_ARCH_SYSTEM_H_
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#ifndef __ASSEMBLY__
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struct exynos4_sysreg {
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unsigned char res1[0x210];
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unsigned int display_ctrl;
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unsigned int display_ctrl2;
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unsigned int camera_control;
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unsigned int audio_endian;
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unsigned int jtag_con;
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};
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struct exynos5_sysreg {
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unsigned char res1[0x214];
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unsigned int disp1blk_cfg;
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unsigned int disp2blk_cfg;
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unsigned int hdcp_e_fuse;
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unsigned int gsclblk_cfg0;
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unsigned int gsclblk_cfg1;
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unsigned int reserved;
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unsigned int ispblk_cfg;
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unsigned int usb20phy_cfg;
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unsigned char res2[0x29c];
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unsigned int mipi_dphy;
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unsigned int dptx_dphy;
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unsigned int phyclk_sel;
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};
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#endif
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#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
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#ifdef CONFIG_EXYNOS5420
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/*
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* Data Synchronization Barrier acts as a special kind of memory barrier.
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* No instruction in program order after this instruction executes until
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* this instruction completes. This instruction completes when:
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* - All explicit memory accesses before this instruction complete.
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* - All Cache, Branch predictor and TLB maintenance operations before
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* this instruction complete.
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*/
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#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
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/*
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* This instruction causes an event to be signaled to all cores
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* within a multiprocessor system. If SEV is implemented,
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* WFE must also be implemented.
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*/
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#define sev() __asm__ __volatile__ ("sev\n\t" : : );
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/*
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* If the Event Register is not set, WFE suspends execution until
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* one of the following events occurs:
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* - an IRQ interrupt, unless masked by the CPSR I-bit
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* - an FIQ interrupt, unless masked by the CPSR F-bit
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* - an Imprecise Data abort, unless masked by the CPSR A-bit
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* - a Debug Entry request, if Debug is enabled
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* - an Event signaled by another processor using the SEV instruction.
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* If the Event Register is set, WFE clears it and returns immediately.
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* If WFE is implemented, SEV must also be implemented.
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*/
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#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
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/* Move 0xd3 value to CPSR register to enable SVC mode */
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#define svc32_mode_en() __asm__ __volatile__ \
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("@ I&F disable, Mode: 0x13 - SVC\n\t" \
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"msr cpsr_c, #0x13|0xC0\n\t" : : )
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/* Set program counter with the given value */
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#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
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/* Read Main Id register */
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#define mrc_midr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
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/* Read Multiprocessor Affinity Register */
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#define mrc_mpafr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
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/* Read System Control Register */
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#define mrc_sctlr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
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/* Read Auxiliary Control Register */
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#define mrc_auxr(x) __asm__ __volatile__ \
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("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
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/* Read L2 Control register */
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#define mrc_l2_ctlr(x) __asm__ __volatile__ \
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("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
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/* Read L2 Auxilliary Control register */
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#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
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("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
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/* Write System Control Register */
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#define mcr_sctlr(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
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/* Write Auxiliary Control Register */
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#define mcr_auxr(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
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/* Invalidate all instruction caches to PoU */
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#define mcr_icache(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
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/* Invalidate unified TLB */
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#define mcr_tlb(x) __asm__ __volatile__ \
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("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
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/* Write L2 Control register */
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#define mcr_l2_ctlr(x) __asm__ __volatile__ \
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("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
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/* Write L2 Auxilliary Control register */
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#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
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("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
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#endif
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void set_usbhost_mode(unsigned int mode);
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void set_system_display_ctrl(void);
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int exynos_lcd_early_init(const void *blob);
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#endif /* _EXYNOS4_SYSTEM_H */
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