mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
7e40e1926a
We can safely remove it, because none of the currently supported
boards uses these features.
The existing implementation had multiple problems:
- unnecessary code duplication between sun4i/sun5i/sun7i
- ZQ calibration was never initiated explicitly, and could be
only triggered by setting the highest bit in the 'zq' parameter
in the 'dram_para' struct (this was never actually done for
any of the known Allwinner devices).
- even if the ZQ calibration could be started, no attempts were
made to wait for its completion, or checking whether the
default automatically initiated ZQ calibration is still
in progress
- ODT was only ever enabled on sun4i, but not on sun5i/sun7i
Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.
The impedance and ODT configuration code will be re-introdeced in
one of the next comits.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
||
|---|---|---|
| .. | ||
| board.c | ||
| clock_sun4i.c | ||
| clock.c | ||
| config.mk | ||
| cpu_info.c | ||
| dram.c | ||
| Makefile | ||
| pinmux.c | ||
| psci.S | ||
| start.c | ||
| timer.c | ||
| u-boot-spl-fel.lds | ||
| u-boot-spl.lds | ||