mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
513 lines
12 KiB
C
513 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Broadcom Corporation.
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*/
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/*
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*
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* bcm281xx architecture clock framework
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <bitfield.h>
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#include <asm/arch/sysmap.h>
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#include <asm/kona-common/clk.h>
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#include "clk-core.h"
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#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
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#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
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#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
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#define POLICY_CTL_GO_ATL 4 /* Active Load */
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/* Helper function */
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int clk_get_and_enable(char *clkstr)
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{
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int ret = 0;
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struct clk *c;
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debug("%s: %s\n", __func__, clkstr);
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c = clk_get(clkstr);
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if (c) {
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ret = clk_enable(c);
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if (ret)
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return ret;
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} else {
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printf("%s: Couldn't find %s\n", __func__, clkstr);
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return -EINVAL;
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}
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return ret;
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}
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/*
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* Poll a register in a CCU's address space, returning when the
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* specified bit in that register's value is set (or clear). Delay
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* a microsecond after each read of the register. Returns true if
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* successful, or false if we gave up trying.
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*
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* Caller must ensure the CCU lock is held.
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*/
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#define CLK_GATE_DELAY_USEC 2000
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static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
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{
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unsigned int tries;
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u32 bit_mask = 1 << bit;
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for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
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u32 val;
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bool bit_val;
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val = readl(base + offset);
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bit_val = (val & bit_mask) ? 1 : 0;
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if (bit_val == want)
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return 0; /* success */
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udelay(1);
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}
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debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
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__func__, base + offset, bit, want);
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return -ETIMEDOUT;
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}
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/* Enable a peripheral clock */
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static int peri_clk_enable(struct clk *c, int enable)
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{
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int ret = 0;
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u32 reg;
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struct peri_clock *peri_clk = to_peri_clk(c);
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struct peri_clk_data *cd = peri_clk->data;
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struct bcm_clk_gate *gate = &cd->gate;
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void *base = (void *)c->ccu_clk_mgr_base;
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debug("%s: %s\n", __func__, c->name);
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clk_get_rate(c); /* Make sure rate and sel are filled in */
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/* enable access */
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writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
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if (enable) {
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debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
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__func__, c->name, c->rate, c->div, c->sel,
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c->parent->rate);
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/*
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* clkgate - only software controllable gates are
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* supported by u-boot which includes all clocks
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* that matter. This avoids bringing in a lot of extra
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* complexity as done in the kernel framework.
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*/
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if (gate_exists(gate)) {
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reg = readl(base + cd->gate.offset);
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reg |= (1 << cd->gate.en_bit);
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writel(reg, base + cd->gate.offset);
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}
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/* div and pll select */
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if (divider_exists(&cd->div)) {
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reg = readl(base + cd->div.offset);
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bitfield_replace(reg, cd->div.shift, cd->div.width,
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c->div - 1);
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writel(reg, base + cd->div.offset);
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}
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/* frequency selector */
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if (selector_exists(&cd->sel)) {
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reg = readl(base + cd->sel.offset);
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bitfield_replace(reg, cd->sel.shift, cd->sel.width,
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c->sel);
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writel(reg, base + cd->sel.offset);
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}
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/* trigger */
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if (trigger_exists(&cd->trig)) {
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writel((1 << cd->trig.bit), base + cd->trig.offset);
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/* wait for trigger status bit to go to 0 */
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ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
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if (ret)
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return ret;
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}
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/* wait for running (status_bit = 1) */
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ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
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if (ret)
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return ret;
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} else {
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debug("%s disable clock %s\n", __func__, c->name);
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/* clkgate */
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reg = readl(base + cd->gate.offset);
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reg &= ~(1 << cd->gate.en_bit);
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writel(reg, base + cd->gate.offset);
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/* wait for stop (status_bit = 0) */
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ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
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}
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/* disable access */
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writel(0, base + WR_ACCESS_OFFSET);
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return ret;
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}
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/* Set the rate of a peripheral clock */
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static int peri_clk_set_rate(struct clk *c, unsigned long rate)
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{
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int ret = 0;
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int i;
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unsigned long diff;
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unsigned long new_rate = 0, div = 1;
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struct peri_clock *peri_clk = to_peri_clk(c);
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struct peri_clk_data *cd = peri_clk->data;
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const char **clock;
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debug("%s: %s\n", __func__, c->name);
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diff = rate;
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i = 0;
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for (clock = cd->clocks; *clock; clock++, i++) {
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struct refclk *ref = refclk_str_to_clk(*clock);
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if (!ref) {
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printf("%s: Lookup of %s failed\n", __func__, *clock);
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return -EINVAL;
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}
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/* round to the new rate */
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div = ref->clk.rate / rate;
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if (div == 0)
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div = 1;
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new_rate = ref->clk.rate / div;
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/* get the min diff */
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if (abs(new_rate - rate) < diff) {
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diff = abs(new_rate - rate);
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c->sel = i;
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c->parent = &ref->clk;
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c->rate = new_rate;
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c->div = div;
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}
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}
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debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
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c->name, c->rate, c->div, c->sel, c->parent->rate);
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return ret;
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}
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/* Get the rate of a peripheral clock */
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static unsigned long peri_clk_get_rate(struct clk *c)
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{
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struct peri_clock *peri_clk = to_peri_clk(c);
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struct peri_clk_data *cd = peri_clk->data;
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void *base = (void *)c->ccu_clk_mgr_base;
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int div = 1;
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const char **clock;
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struct refclk *ref;
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u32 reg;
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debug("%s: %s\n", __func__, c->name);
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if (selector_exists(&cd->sel)) {
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reg = readl(base + cd->sel.offset);
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c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
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} else {
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/*
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* For peri clocks that don't have a selector, the single
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* reference clock will always exist at index 0.
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*/
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c->sel = 0;
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}
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if (divider_exists(&cd->div)) {
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reg = readl(base + cd->div.offset);
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div = bitfield_extract(reg, cd->div.shift, cd->div.width);
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div += 1;
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}
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clock = cd->clocks;
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ref = refclk_str_to_clk(clock[c->sel]);
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if (!ref) {
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printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
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return 0;
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}
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c->parent = &ref->clk;
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c->div = div;
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c->rate = c->parent->rate / c->div;
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debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
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c->parent->rate, div, c->sel, c->rate);
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return c->rate;
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}
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/* Peripheral clock operations */
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struct clk_ops peri_clk_ops = {
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.enable = peri_clk_enable,
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.set_rate = peri_clk_set_rate,
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.get_rate = peri_clk_get_rate,
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};
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/* Enable a CCU clock */
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static int ccu_clk_enable(struct clk *c, int enable)
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{
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struct ccu_clock *ccu_clk = to_ccu_clk(c);
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void *base = (void *)c->ccu_clk_mgr_base;
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int ret = 0;
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u32 reg;
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debug("%s: %s\n", __func__, c->name);
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if (!enable)
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return -EINVAL; /* CCU clock cannot shutdown */
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/* enable access */
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writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
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/* config enable for policy engine */
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writel(1, base + ccu_clk->lvm_en_offset);
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/* wait for bit to go to 0 */
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ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
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if (ret)
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return ret;
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/* freq ID */
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if (!ccu_clk->freq_bit_shift)
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ccu_clk->freq_bit_shift = 8;
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/* Set frequency id for each of the 4 policies */
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reg = ccu_clk->freq_id |
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(ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
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(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
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(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
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writel(reg, base + ccu_clk->policy_freq_offset);
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/* enable all clock mask */
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writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
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writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
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writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
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writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
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if (ccu_clk->num_policy_masks == 2) {
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writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
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writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
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writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
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writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
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}
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/* start policy engine */
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reg = readl(base + ccu_clk->policy_ctl_offset);
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reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
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writel(reg, base + ccu_clk->policy_ctl_offset);
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/* wait till started */
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ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
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if (ret)
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return ret;
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/* disable access */
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writel(0, base + WR_ACCESS_OFFSET);
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return ret;
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}
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/* Get the CCU clock rate */
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static unsigned long ccu_clk_get_rate(struct clk *c)
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{
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struct ccu_clock *ccu_clk = to_ccu_clk(c);
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debug("%s: %s\n", __func__, c->name);
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c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
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return c->rate;
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}
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/* CCU clock operations */
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struct clk_ops ccu_clk_ops = {
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.enable = ccu_clk_enable,
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.get_rate = ccu_clk_get_rate,
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};
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/* Enable a bus clock */
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static int bus_clk_enable(struct clk *c, int enable)
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{
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struct bus_clock *bus_clk = to_bus_clk(c);
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struct bus_clk_data *cd = bus_clk->data;
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void *base = (void *)c->ccu_clk_mgr_base;
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int ret = 0;
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u32 reg;
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debug("%s: %s\n", __func__, c->name);
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/* enable access */
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writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
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/* enable gating */
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reg = readl(base + cd->gate.offset);
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if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
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debug("%s already %s\n", c->name,
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enable ? "enabled" : "disabled");
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else {
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int want = (enable) ? 1 : 0;
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reg |= (1 << cd->gate.hw_sw_sel_bit);
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if (enable)
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reg |= (1 << cd->gate.en_bit);
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else
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reg &= ~(1 << cd->gate.en_bit);
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writel(reg, base + cd->gate.offset);
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ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
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want);
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if (ret)
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return ret;
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}
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/* disable access */
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writel(0, base + WR_ACCESS_OFFSET);
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return ret;
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}
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/* Get the rate of a bus clock */
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static unsigned long bus_clk_get_rate(struct clk *c)
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{
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struct bus_clock *bus_clk = to_bus_clk(c);
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struct ccu_clock *ccu_clk;
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debug("%s: %s\n", __func__, c->name);
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ccu_clk = to_ccu_clk(c->parent);
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c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
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c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
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return c->rate;
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}
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/* Bus clock operations */
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struct clk_ops bus_clk_ops = {
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.enable = bus_clk_enable,
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.get_rate = bus_clk_get_rate,
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};
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/* Enable a reference clock */
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static int ref_clk_enable(struct clk *c, int enable)
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{
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debug("%s: %s\n", __func__, c->name);
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return 0;
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}
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/* Reference clock operations */
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struct clk_ops ref_clk_ops = {
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.enable = ref_clk_enable,
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};
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/*
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* clk.h implementation follows
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*/
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/* Initialize the clock framework */
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int clk_init(void)
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{
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debug("%s:\n", __func__);
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return 0;
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}
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/* Get a clock handle, give a name string */
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struct clk *clk_get(const char *con_id)
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{
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int i;
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struct clk_lookup *clk_tblp;
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debug("%s: %s\n", __func__, con_id);
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clk_tblp = arch_clk_tbl;
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for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
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if (clk_tblp->con_id) {
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if (!con_id || strcmp(clk_tblp->con_id, con_id))
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continue;
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return clk_tblp->clk;
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}
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}
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return NULL;
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}
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/* Enable a clock */
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int clk_enable(struct clk *c)
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{
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int ret = 0;
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debug("%s: %s\n", __func__, c->name);
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if (!c->ops || !c->ops->enable)
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return -1;
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/* enable parent clock first */
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if (c->parent)
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ret = clk_enable(c->parent);
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if (ret)
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return ret;
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if (!c->use_cnt) {
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c->use_cnt++;
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ret = c->ops->enable(c, 1);
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}
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return ret;
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}
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/* Disable a clock */
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void clk_disable(struct clk *c)
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{
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debug("%s: %s\n", __func__, c->name);
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if (!c->ops || !c->ops->enable)
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return;
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if (c->use_cnt) {
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c->use_cnt--;
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c->ops->enable(c, 0);
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}
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/* disable parent */
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if (c->parent)
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clk_disable(c->parent);
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}
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/* Get the clock rate */
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unsigned long clk_get_rate(struct clk *c)
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{
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unsigned long rate;
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if (!c || !c->ops || !c->ops->get_rate)
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return 0;
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debug("%s: %s\n", __func__, c->name);
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rate = c->ops->get_rate(c);
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debug("%s: rate = %ld\n", __func__, rate);
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return rate;
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}
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/* Set the clock rate */
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int clk_set_rate(struct clk *c, unsigned long rate)
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{
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int ret;
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if (!c || !c->ops || !c->ops->set_rate)
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return -EINVAL;
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debug("%s: %s rate=%ld\n", __func__, c->name, rate);
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if (c->use_cnt)
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return -EINVAL;
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ret = c->ops->set_rate(c, rate);
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return ret;
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}
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/* Not required for this arch */
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/*
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long clk_round_rate(struct clk *clk, unsigned long rate);
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int clk_set_parent(struct clk *clk, struct clk *parent);
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struct clk *clk_get_parent(struct clk *clk);
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*/
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