mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 15:53:21 +09:00
2b5b2be5e9
At this time I2C and responsible pin-mux is setup during PMIC initialziation within common.c, this is possible because today PMIC is always connected on I2C0. In Future this will be changed, PMIC isn't anymore connected to bus0 in call cases. So we do following: - rename enable_i2c_pin_mux0 to enable_i2c_pin_mux to be generic for enabling pin-mux on different or more busses. - move the call to i2c_pin_mux and i2c_init from common.c to the specific board.c Signed-off-by: Hannes Petermaier <hannes.petermaier@br-automation.com> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
318 lines
8.6 KiB
C
318 lines
8.6 KiB
C
/*
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* board.c
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*
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* Board functions for B&R KWB Board
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*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include <lcd.h>
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/* -------------------------------------------------------------------------*/
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/* -- defines for used GPIO Hardware -- */
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#define ESC_KEY (0+19)
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#define LCD_PWR (0+5)
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#define PUSH_KEY (0+31)
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/* -------------------------------------------------------------------------*/
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/* -- PSOC Resetcontroller Register defines -- */
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/* I2C Address of controller */
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#define RSTCTRL_ADDR 0x75
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/* Register for CTRL-word */
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#define RSTCTRL_CTRLREG 0x01
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/* Register for giving some information to VxWorks OS */
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#define RSTCTRL_SCRATCHREG 0x04
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/* -- defines for RSTCTRL_CTRLREG -- */
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#define RSTCTRL_FORCE_PWR_NEN 0x0404
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#define RSTCTRL_CAN_STB 0x4040
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#define VXWORKS_BOOTLINE 0x80001100
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#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
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#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD)
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/* TODO: check ram-timing ! */
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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unsigned int oldspeed;
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unsigned short buf;
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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/*
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* enable additional clocks of modules which are accessed later from
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* VxWorks OS
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*/
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u32 *const clk_domains[] = { 0 };
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u32 *const clk_modules_kwbspecific[] = {
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&cmwkup->wkup_adctscctrl,
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&cmper->spi1clkctrl,
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&cmper->dcan0clkctrl,
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&cmper->dcan1clkctrl,
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&cmper->epwmss0clkctrl,
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&cmper->epwmss1clkctrl,
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&cmper->epwmss2clkctrl,
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
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/* setup LCD-Pixel Clock */
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writel(0x2, CM_DPLL + 0x34);
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/* power-OFF LCD-Display */
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gpio_direction_output(LCD_PWR, 0);
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/* setup I2C */
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enable_i2c_pin_mux();
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i2c_set_bus_num(0);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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/* power-ON 3V3 via Resetcontroller */
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oldspeed = i2c_get_bus_speed();
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if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
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buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
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i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
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(uint8_t *)&buf, sizeof(buf));
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i2c_set_bus_speed(oldspeed);
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} else {
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puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
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}
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pmicsetup(0);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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const unsigned int toff = 1000;
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unsigned int cnt = 3;
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unsigned short buf = 0xAAAA;
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unsigned char scratchreg = 0;
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unsigned int oldspeed;
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/* try to read out some boot-instruction from resetcontroller */
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oldspeed = i2c_get_bus_speed();
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if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
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i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
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&scratchreg, sizeof(scratchreg));
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i2c_set_bus_speed(oldspeed);
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} else {
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puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
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}
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if (gpio_get_value(ESC_KEY)) {
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do {
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lcd_position_cursor(1, 8);
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switch (cnt) {
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case 3:
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lcd_puts(
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"release ESC-KEY to enter SERVICE-mode.");
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break;
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case 2:
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lcd_puts(
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"release ESC-KEY to enter DIAGNOSE-mode.");
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break;
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case 1:
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lcd_puts(
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"release ESC-KEY to enter BOOT-mode. ");
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break;
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}
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mdelay(toff);
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cnt--;
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if (!gpio_get_value(ESC_KEY) &&
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gpio_get_value(PUSH_KEY) && 2 == cnt) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"switching to network-console ... ");
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setenv("bootcmd", "run netconsole");
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cnt = 4;
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break;
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} else if (!gpio_get_value(ESC_KEY) &&
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gpio_get_value(PUSH_KEY) && 1 == cnt) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"updating U-BOOT from USB ... ");
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setenv("bootcmd", "run usbupdate");
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cnt = 4;
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break;
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} else if ((!gpio_get_value(ESC_KEY) &&
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gpio_get_value(PUSH_KEY) && cnt == 0) ||
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(gpio_get_value(ESC_KEY) &&
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gpio_get_value(PUSH_KEY) && cnt == 0)) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"starting script from network ... ");
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setenv("bootcmd", "run netscript");
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cnt = 4;
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break;
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} else if (!gpio_get_value(ESC_KEY)) {
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break;
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}
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} while (cnt);
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} else if (scratchreg == 0xCC) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"starting vxworks from network ... ");
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setenv("bootcmd", "run netboot");
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cnt = 4;
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} else if (scratchreg == 0xCD) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"starting script from network ... ");
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setenv("bootcmd", "run netscript");
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cnt = 4;
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} else if (scratchreg == 0xCE) {
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lcd_position_cursor(1, 8);
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lcd_puts(
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"starting AR from eMMC ... ");
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setenv("bootcmd", "run mmcboot");
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cnt = 4;
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}
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lcd_position_cursor(1, 8);
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switch (cnt) {
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case 0:
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lcd_puts("entering BOOT-mode. ");
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setenv("bootcmd", "run defaultAR");
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buf = 0x0000;
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break;
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case 1:
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lcd_puts("entering DIAGNOSE-mode. ");
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buf = 0x0F0F;
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break;
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case 2:
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lcd_puts("entering SERVICE mode. ");
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buf = 0xB4B4;
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break;
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case 3:
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lcd_puts("loading OS... ");
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buf = 0x0404;
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break;
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}
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/* write bootinfo into scratchregister of resetcontroller */
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oldspeed = i2c_get_bus_speed();
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if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
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i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
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(uint8_t *)&buf, sizeof(buf));
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i2c_set_bus_speed(oldspeed);
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} else {
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puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
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}
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/* setup vxworks bootline */
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char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
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/* setup default IP, in case if there is nothing in environment */
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if (!getenv("ipaddr")) {
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setenv("ipaddr", "192.168.60.1");
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setenv("netmask", "255.255.255.0");
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setenv("serverip", "192.168.60.254");
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setenv("gatewayip", "192.168.60.254");
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puts("net: had no IP! made default setup.\n");
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}
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sprintf(vxworksbootline,
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"%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
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DEFAULT_BOOTLINE,
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getenv("serverip"),
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getenv("ipaddr"), getenv("netmask"),
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getenv("gatewayip"),
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VXWORKS_USER,
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(unsigned int) gd->fb_base-0x20,
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(u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
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(u32)getenv_ulong("vx_romfsbase", 16, 0),
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(u32)getenv_ulong("vx_romfssize", 16, 0));
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/*
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* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
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* expect that vectors are there, original u-boot moves them to _start
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*/
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__asm__("ldr r0,=0x20000");
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__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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