mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 13:53:44 +09:00
7dad444c76
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA drive strength has caused CE test to fail. This requires changes on the pad skew for EMAC0 PHY driver. Based on several measurements done, Tx clock does not require the extra 0.96ns delay which was needed in Arria10. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
139 lines
2.3 KiB
Plaintext
Executable File
139 lines
2.3 KiB
Plaintext
Executable File
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Intel Corporation
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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model = "SoCFPGA Stratix 10 SoCDK";
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aliases {
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i2c0 = &i2c1;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* 4GB */
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reg = <0 0x00000000 0 0x80000000>,
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<1 0x80000000 0 0x80000000>;
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u-boot,dm-pre-reloc;
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <3800>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <900>; /* 0ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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drvsel = <3>;
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smplsel = <0>;
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};
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&qspi {
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00a";
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reg = <0>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <1>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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qspi_boot: partition@0 {
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label = "Boot and fpga data";
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reg = <0x0 0x4000000>;
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};
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qspi_rootfs: partition@4000000 {
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label = "Root Filesystem - JFFS2";
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reg = <0x4000000 0x4000000>;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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