mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
8a490422be
MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash and CPLD on the ADS5121. This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD) it does so conditionally based on silicon rev 2.0 or greater. Signed-off-by: Martha J Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
493 lines
15 KiB
C
493 lines
15 KiB
C
/*
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* (C) Copyright 2007, 2008 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* ADS5121 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ADS5121 1
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/*
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* Memory map for the ADS5121 board:
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*
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* 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
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* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
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* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
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* 0x8200_0000 - 0x8200_001F CPLD (32 B)
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* 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
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* 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
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* 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
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* 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
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*/
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC512X 1 /* MPC512X family */
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#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
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/* video */
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#undef CONFIG_VIDEO
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#if defined(CONFIG_VIDEO)
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#endif
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/* CONFIG_PCI is defined at config time */
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
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#else
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#define CFG_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_PCI
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CFG_IMMR 0x80000000
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#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
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#define CFG_MEMTEST_START 0x00200000 /* memtest region */
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#define CFG_MEMTEST_END 0x00400000
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/*
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* DDR Setup - manually set all parameters as there's no SPD etc.
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*/
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_DDR_SIZE 256 /* MB */
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#else
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#define CFG_DDR_SIZE 512 /* MB */
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#endif
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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/* DDR Controller Configuration
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
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* [30:30] DRAM CKE pin: Enabled
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* [29:29] DRAM CLK: Enabled
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* [28:28] Command Mode: Enabled (For initialization only)
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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* [20:19] Read Test: DON'T USE
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* [18:18] Self Refresh: Enabled
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* [17:17] 16bit Mode: Disabled
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* [16:13] Ready Delay: 2
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* [12:12] Half DQS Delay: Disabled
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* [11:11] Quarter DQS Delay: Disabled
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* [10:08] Write Delay: 2
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* [07:07] Early ODT: Disabled
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* [06:06] On DIE Termination: Disabled
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* [05:05] FIFO Overflow Clear: DON'T USE here
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* [04:04] FIFO Underflow Clear: DON'T USE here
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* [03:03] FIFO Overflow Pending: DON'T USE here
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* [02:02] FIFO Underlfow Pending: DON'T USE here
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* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
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* [15:8] DRAM Command Time: 0 CSB clocks
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* [07:00] DRAM Precharge Time: 0 CSB clocks
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* TIME_CFG1
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* [31:26] DRAM tRFC:
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* [25:21] DRAM tWR1:
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
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* [10:05] DRAM tRC:
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* [04:00] DRAM tRAS:
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* TIME_CFG2
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* [31:28] DRAM tRCD:
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* [27:23] DRAM tFAW:
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* [22:19] DRAM tRTW1:
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* [18:15] DRAM tCCD:
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* [14:10] DRAM tRTP:
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_MDDRC_SYS_CFG 0xF8604A00
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#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
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#define CFG_MDDRC_TIME_CFG1 0x54EC1168
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#define CFG_MDDRC_TIME_CFG2 0x35210864
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#else
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#define CFG_MDDRC_SYS_CFG 0xFA804A00
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#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00
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#define CFG_MDDRC_TIME_CFG1 0x68EC1168
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#define CFG_MDDRC_TIME_CFG2 0x34310864
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#endif
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#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
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#define CFG_MDDRC_TIME_CFG0 0x00003D2E
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#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
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#define CFG_MICRON_NOP 0x01380000
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#define CFG_MICRON_PCHG_ALL 0x01100400
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#define CFG_MICRON_EM2 0x01020000
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#define CFG_MICRON_EM3 0x01030000
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#define CFG_MICRON_EN_DLL 0x01010000
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#define CFG_MICRON_RFSH 0x01080000
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#define CFG_MICRON_INIT_DEV_OP 0x01000432
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#define CFG_MICRON_OCD_DEFAULT 0x01010780
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/* DDR Priority Manager Configuration */
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#define CFG_MDDRCGRP_PM_CFG1 0x00077777
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#define CFG_MDDRCGRP_PM_CFG2 0x00000000
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#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
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#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
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#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
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#define CFG_MDDRCGRP_LUT1_MU 0x66666666
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#define CFG_MDDRCGRP_LUT1_ML 0x55555555
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#define CFG_MDDRCGRP_LUT2_MU 0x44444444
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#define CFG_MDDRCGRP_LUT2_ML 0x44444444
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#define CFG_MDDRCGRP_LUT3_MU 0x55555555
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#define CFG_MDDRCGRP_LUT3_ML 0x55555558
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#define CFG_MDDRCGRP_LUT4_MU 0x11111111
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#define CFG_MDDRCGRP_LUT4_ML 0x11111122
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#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
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#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
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#define CFG_MDDRCGRP_LUT1_AU 0x66666666
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#define CFG_MDDRCGRP_LUT1_AL 0x66666666
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#define CFG_MDDRCGRP_LUT2_AU 0x11111111
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#define CFG_MDDRCGRP_LUT2_AL 0x11111111
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#define CFG_MDDRCGRP_LUT3_AU 0x11111111
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#define CFG_MDDRCGRP_LUT3_AL 0x11111111
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#define CFG_MDDRCGRP_LUT4_AU 0x11111111
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#define CFG_MDDRCGRP_LUT4_AL 0x11111111
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/*
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* NOR FLASH on the Local Bus
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*/
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#undef CONFIG_BKUP_FLASH
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#ifdef CONFIG_BKUP_FLASH
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#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
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#define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */
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#else
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#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
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#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
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#endif
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#define CFG_FLASH_USE_BUFFER_WRITE
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CFG_FLASH_CHECKSUM
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/*
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* CPLD registers area is really only 32 bytes in size, but the smallest possible LP
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* window is 64KB
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*/
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#define CFG_CPLD_BASE 0x82000000
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#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
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#define CFG_SRAM_BASE 0x30000000
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#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
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#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
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#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
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#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
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/* Use SRAM for initial stack */
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#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
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#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#ifdef CONFIG_FSL_DIU_FB
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#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
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#else
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#define CFG_MALLOC_LEN (512 * 1024)
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#endif
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
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#if CONFIG_PSC_CONSOLE != 3
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#error CONFIG_PSC_CONSOLE must be 3
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#endif
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
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#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* PCI
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*/
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#ifdef CONFIG_PCI
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/*
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* General PCI
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*/
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#define CFG_PCI_MEM_BASE 0xA0000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
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#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
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#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
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#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_IO_BASE 0x00000000
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#define CFG_PCI_IO_PHYS 0x84000000
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#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#if 0
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#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
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#endif
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/*
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* EEPROM configuration
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*/
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
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#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC512x_FEC 1
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_ADDR 0x1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_FEC_AN_TIMEOUT 1
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#define CONFIG_HAS_ETH0
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* Environment
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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/* This has to be a multiple of the Flash sector size */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_SIZE 0x2000
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#ifdef CONFIG_BKUP_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
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#else
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#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
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#endif
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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/*
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* Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
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* For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
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* to 0xFFFF, watchdog timeouts after about 64s. For details refer
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* to chapter 36 of the MPC5121e Reference Manual.
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*/
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/* #define CONFIG_WATCHDOG */ /* enable watchdog */
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#define CFG_WATCHDOG_VALUE 0xFFFF
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#ifdef CONFIG_CMD_KGDB
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/* Cache Configuration */
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#define CFG_DCACHE_SIZE 32768
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#define CFG_CACHELINE_SIZE 32
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#ifdef CONFIG_CMD_KGDB
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#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
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#endif
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#define CFG_HID0_INIT 0x000000000
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#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
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#define CFG_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_TIMESTAMP
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#define CONFIG_HOSTNAME ads5121
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#define CONFIG_BOOTFILE ads5121/uImage
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#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
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#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u-boot_addr_r=200000\0" \
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"kernel_addr_r=600000\0" \
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"fdt_addr_r=880000\0" \
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|
"ramdisk_addr_r=900000\0" \
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|
"u-boot_addr=FFF00000\0" \
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|
"kernel_addr=FFC40000\0" \
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|
"fdt_addr=FFEC0000\0" \
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|
"ramdisk_addr=FC040000\0" \
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|
"ramdiskfile=ads5121/uRamdisk\0" \
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|
"u-boot=ads5121/u-boot.bin\0" \
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|
"bootfile=ads5121/uImage\0" \
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|
"fdtfile=ads5121/ads5121.dtb\0" \
|
|
"rootpath=/opt/eldk/ppc_6xx\n" \
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|
"netdev=eth0\0" \
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|
"consdev=ttyPSC0\0" \
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|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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|
":${hostname}:${netdev}:off panic=1\0" \
|
|
"addtty=setenv bootargs ${bootargs} " \
|
|
"console=${consdev},${baudrate}\0" \
|
|
"flash_nfs=run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
|
"flash_self=run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
|
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
|
"tftp ${fdt_addr_r} ${fdtfile};" \
|
|
"run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
|
"net_self=tftp ${kernel_addr_r} ${bootfile};" \
|
|
"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
|
|
"tftp ${fdt_addr_r} ${fdtfile};" \
|
|
"run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
|
|
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
|
|
"update=protect off ${u-boot_addr} +${filesize};" \
|
|
"era ${u-boot_addr} +${filesize};" \
|
|
"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
|
|
"upd=run load update\0" \
|
|
""
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
|
|
#define CONFIG_OF_LIBFDT 1
|
|
#define CONFIG_OF_BOARD_SETUP 1
|
|
#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
|
|
|
|
#define OF_CPU "PowerPC,5121@0"
|
|
#define OF_SOC_COMPAT "fsl,mpc5121-immr"
|
|
#define OF_TBCLK (bd->bi_busfreq / 4)
|
|
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
|
|
|
|
#endif /* __CONFIG_H */
|