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https://github.com/brain-hackers/u-boot-brain
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5f7f70c171
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* Register definitions for Freescale QSPI
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_QSPI_H_
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#define _FSL_QSPI_H_
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struct fsl_qspi_regs {
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u32 mcr;
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u32 rsvd0[1];
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u32 ipcr;
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u32 flshcr;
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u32 buf0cr;
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u32 buf1cr;
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u32 buf2cr;
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u32 buf3cr;
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u32 bfgencr;
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u32 soccr;
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u32 rsvd1[2];
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u32 buf0ind;
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u32 buf1ind;
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u32 buf2ind;
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u32 rsvd2[49];
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u32 sfar;
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u32 rsvd3[1];
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u32 smpr;
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u32 rbsr;
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u32 rbct;
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u32 rsvd4[15];
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u32 tbsr;
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u32 tbdr;
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u32 rsvd5[1];
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u32 sr;
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u32 fr;
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u32 rser;
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u32 spndst;
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u32 sptrclr;
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u32 rsvd6[4];
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u32 sfa1ad;
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u32 sfa2ad;
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u32 sfb1ad;
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u32 sfb2ad;
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u32 rsvd7[28];
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u32 rbdr[32];
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u32 rsvd8[32];
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u32 lutkey;
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u32 lckcr;
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u32 rsvd9[2];
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u32 lut[64];
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};
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#define QSPI_IPCR_SEQID_SHIFT 24
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#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
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#define QSPI_MCR_END_CFD_SHIFT 2
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#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
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#ifdef CONFIG_SYS_FSL_QSPI_AHB
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/* AHB needs 64bit operation */
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#define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT)
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#else
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#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
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#endif
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#define QSPI_MCR_DDR_EN_SHIFT 7
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#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
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#define QSPI_MCR_CLR_RXF_SHIFT 10
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#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
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#define QSPI_MCR_CLR_TXF_SHIFT 11
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#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
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#define QSPI_MCR_MDIS_SHIFT 14
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#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
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#define QSPI_MCR_RESERVED_SHIFT 16
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#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
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#define QSPI_MCR_SWRSTHD_SHIFT 1
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#define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT)
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#define QSPI_MCR_SWRSTSD_SHIFT 0
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#define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT)
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#define QSPI_SMPR_HSENA_SHIFT 0
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#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
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#define QSPI_SMPR_FSPHS_SHIFT 5
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#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
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#define QSPI_SMPR_FSDLY_SHIFT 6
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#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
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#define QSPI_SMPR_DDRSMP_SHIFT 16
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#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
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#define QSPI_BUFXCR_INVALID_MSTRID 0xe
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#define QSPI_BUF3CR_ALLMST_SHIFT 31
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#define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT)
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#define QSPI_BUF3CR_ADATSZ_SHIFT 8
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#define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
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#define QSPI_BFGENCR_SEQID_SHIFT 12
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#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
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#define QSPI_BFGENCR_PAR_EN_SHIFT 16
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#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
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#define QSPI_RBSR_RDBFL_SHIFT 8
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#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
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#define QSPI_RBCT_RXBRD_SHIFT 8
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#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
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#define QSPI_SR_BUSY_SHIFT 0
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#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
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#define QSPI_LCKCR_LOCK 0x1
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#define QSPI_LCKCR_UNLOCK 0x2
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#define LUT_KEY_VALUE 0x5af05af0
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#define OPRND0_SHIFT 0
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#define OPRND0(x) ((x) << OPRND0_SHIFT)
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#define PAD0_SHIFT 8
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#define PAD0(x) ((x) << PAD0_SHIFT)
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#define INSTR0_SHIFT 10
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#define INSTR0(x) ((x) << INSTR0_SHIFT)
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#define OPRND1_SHIFT 16
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#define OPRND1(x) ((x) << OPRND1_SHIFT)
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#define PAD1_SHIFT 24
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#define PAD1(x) ((x) << PAD1_SHIFT)
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#define INSTR1_SHIFT 26
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#define INSTR1(x) ((x) << INSTR1_SHIFT)
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#define LUT_CMD 1
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#define LUT_ADDR 2
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#define LUT_DUMMY 3
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#define LUT_READ 7
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#define LUT_WRITE 8
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#define LUT_PAD1 0
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#define LUT_PAD2 1
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#define LUT_PAD4 2
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#define ADDR24BIT 0x18
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#define ADDR32BIT 0x20
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#endif /* _FSL_QSPI_H_ */
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