mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
a4d2636f2a
The update procedure was modified to turn off the USB subsystem before exit for MCC200 and TRAB. This is necessary as otherwise the USB controller continues to write periodically to system memory! MCC200-specific notes: - the patch disables the magic key check for MCC200 - the patch contains the configuration changes made for the new revision of the board. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
420 lines
12 KiB
C
420 lines
12 KiB
C
/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MCC200 1 /* ... on MCC200 board */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
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#define CONFIG_MISC_INIT_R
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Serial console configuration
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*
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* To select console on the one of 8 external UARTs,
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* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
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* or as 5, 6, 7, or 8 for the second Quad UART.
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* COM11, COM12, COM13, COM14 are located on the second Quad UART.
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*
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* CONFIG_PSC_CONSOLE must be undefined in this case.
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*/
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#if !defined(CONFIG_PRS200)
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/* MCC200 configuration: */
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#ifdef CONFIG_CONSOLE_COM12
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#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
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#else
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#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
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#endif
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#else
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/* PRS200 configuration: */
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#undef CONFIG_QUART_CONSOLE
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#endif /* CONFIG_PRS200 */
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/*
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* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
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* and undefine CONFIG_QUART_CONSOLE.
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*/
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#if !defined(CONFIG_PRS200)
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/* MCC200 configuration: */
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
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#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
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#else
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/* PRS200 configuration: */
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#endif
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#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
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!defined(CONFIG_SERIAL_MULTI)
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#error "Select only one console device!"
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_MII 1
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#define CONFIG_DOS_PARTITION
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* automatic software updates (see board/mcc200/auto_update.c) */
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#define CONFIG_AUTO_UPDATE 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_USB
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#undef CONFIG_CMD_NET
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define XMK_STR(x) #x
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#define MK_STR(x) XMK_STR(x)
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#ifdef CONFIG_PRS200
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# define CFG__BOARDNAME "prs200"
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# define CFG__LINUX_CONSOLE "ttyS0"
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#else
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# define CFG__BOARDNAME "mcc200"
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# define CFG__LINUX_CONSOLE "ttyEU5"
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#endif
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/* Network */
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#define CONFIG_ETHADDR 00:17:17:ff:00:00
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#define CONFIG_IPADDR 10.76.9.29
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#define CONFIG_SERVERIP 10.76.9.1
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#include <version.h> /* For U-Boot version */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ubootver=" U_BOOT_VERSION "\0" \
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"netdev=eth0\0" \
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"hostname=" CFG__BOARDNAME "\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/mtdblock2 " \
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"rootfstype=cramfs\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addcons=setenv bootargs ${bootargs} " \
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"console=${console},${baudrate} " \
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"ubootver=${ubootver} board=${board}\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addcons;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addcons;bootm\0" \
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"console=" CFG__LINUX_CONSOLE "\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
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"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
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"text_base=" MK_STR(TEXT_BASE) "\0" \
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"kernel_addr=0xFC0C0000\0" \
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"update=protect off ${text_base} +${filesize};" \
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"era ${text_base} +${filesize};" \
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"cp.b 200000 ${text_base} ${filesize}\0" \
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"unlock=yes\0" \
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""
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#undef MK_STR
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#undef XMK_STR
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
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#define CFG_PROMPT_HUSH_PS2 "> "
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/*
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* IPB Bus clocking configuration.
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*/
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#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* Flash configuration (8,16 or 32 MB)
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* TEXT base always at 0xFFF00000
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* ENV_ADDR always at 0xFFF40000
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* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
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* 0xFE000000 for 32 MB
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* 0xFF000000 for 16 MB
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* 0xFF800000 for 8 MB
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*/
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#define CFG_FLASH_BASE 0xfc000000
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#define CFG_FLASH_SIZE 0x04000000
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
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#if TEXT_BASE == CFG_FLASH_BASE
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#define CFG_LOWBOOT 1
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#endif
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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/*#define CONFIG_MPC5xxx_FEC 1*/
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/*
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* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
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*/
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/* #define CONFIG_FEC_10MBIT 1 */
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#define CONFIG_PHY_ADDR 1
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/*
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* LCD Splash Screen
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*/
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#if !defined(CONFIG_PRS200)
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#define CONFIG_LCD 1
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#define CONFIG_PROGRESSBAR 1
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#endif
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#if defined(CONFIG_LCD)
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#define CONFIG_SPLASH_SCREEN 1
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#define CFG_CONSOLE_IS_IN_ENV 1
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#define LCD_BPP LCD_MONOCHROME
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#endif
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/*
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* GPIO configuration
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*/
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/* 0x10000004 = 32MB SDRAM */
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/* 0x90000004 = 64MB SDRAM */
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#if defined(CONFIG_LCD)
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/* set PSC2 in UART mode */
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#define CFG_GPS_PORT_CONFIG 0x00000044
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#else
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#define CFG_GPS_PORT_CONFIG 0x00000004
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#define CFG_BOOTCS_CFG 0x0004fb00
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
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#define CFG_CS2_START 0x80000000
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#define CFG_CS2_SIZE 0x00001000
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#define CFG_CS2_CFG 0x1d300
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/* Second Quad UART @0x80010000 */
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#define CFG_CS1_START 0x80010000
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#define CFG_CS1_SIZE 0x00001000
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#define CFG_CS1_CFG 0x1d300
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/* Leica - build revision resistors */
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/*
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#define CFG_CS3_START 0x80020000
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#define CFG_CS3_SIZE 0x00000004
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#define CFG_CS3_CFG 0x1d300
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*/
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/*
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* Select one of quarts as a default
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* console. If undefined - PSC console
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* wil be default
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*/
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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#define CFG_RESET_ADDRESS 0xff000000
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/*
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* QUART Expanders support
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*/
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#if defined(CONFIG_QUART_CONSOLE)
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/*
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* We'll use NS16550 chip routines,
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*/
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#define CFG_NS16550 1
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#define CFG_NS16550_SERIAL 1
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#define CONFIG_CONS_INDEX 1
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/*
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* To achieve necessary offset on SC16C554
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* A0-A2 (register select) pins with NS16550
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* functions (in struct NS16550), REG_SIZE
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* should be 4, because A0-A2 pins are connected
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* to DA2-DA4 address bus lines.
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*/
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#define CFG_NS16550_REG_SIZE 4
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/*
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* LocalPlus Bus already inited in cpu_init_f(),
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* so can work with QUART's chip selects.
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* One of four SC16C554 UARTs is selected with
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* A3-A4 (DA5-DA6) lines.
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*/
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#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
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#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
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#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
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#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
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#elif
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#error "Wrong QUART expander number."
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#endif
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/*
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* SC16C554 chip's external crystal oscillator frequency
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* is 7.3728 MHz
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*/
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#define CFG_NS16550_CLK 7372800
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#endif /* CONFIG_QUART_CONSOLE */
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00005000
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#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
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#define CONFIG_AUTOBOOT_STOP_STR "432"
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#define CONFIG_SILENT_CONSOLE 1
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#endif /* __CONFIG_H */
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