mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
87 lines
1.8 KiB
C
87 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
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(((segbus) & 0xfff) << 20) | \
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(((dev) & 0x1f) << 15) | \
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(((fn) & 0x07) << 12))
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/* Platform Controller Unit */
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#define LPC_DEV 0x1f
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#define LPC_FUNC 0
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/* Enable UART */
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#define UART_CONT 0x80
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/* SCORE Pad definitions */
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#define UART_RXD_PAD 82
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#define UART_TXD_PAD 83
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/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
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#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed0c000
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#define IO_BASE_OFFSET_GPSCORE 0x0000
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#define IO_BASE_OFFSET_GPNCORE 0x1000
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#define IO_BASE_OFFSET_GPSSUS 0x2000
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#define IO_BASE_SIZE 0x4000
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static inline unsigned int score_pconf0(int pad_num)
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{
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return GPSCORE_PAD_BASE + pad_num * 16;
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}
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static void score_select_func(int pad, int func)
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{
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uint32_t reg;
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uint32_t pconf0_addr = score_pconf0(pad);
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reg = readl(pconf0_addr);
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reg &= ~0x7;
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reg |= func & 0x7;
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writel(reg, pconf0_addr);
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}
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static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
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{
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unsigned long addr;
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addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
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writel(value, addr);
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}
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/* This can be called after memory-mapped PCI is working */
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int setup_internal_uart(int enable)
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{
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/* Enable or disable the legacy UART hardware */
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x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
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enable);
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/* All done for the disable part, so just return */
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if (!enable)
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return 0;
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/*
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* Set up the pads to the UART function. This allows the signals to
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* leave the chip
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*/
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score_select_func(UART_RXD_PAD, 1);
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score_select_func(UART_TXD_PAD, 1);
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/* TODO(sjg@chromium.org): Call debug_uart_init() */
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return 0;
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}
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void board_debug_uart_init(void)
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{
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setup_internal_uart(1);
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}
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