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![Thomas Abraham](/assets/img/avatar_default.png)
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
177 lines
3.7 KiB
C
177 lines
3.7 KiB
C
/*
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* Mem setup common file for different types of DDR present on Exynos boards.
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/spl.h>
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#include "clock_init.h"
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#include "common_setup.h"
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#include "exynos5_setup.h"
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#define ZQ_INIT_TIMEOUT 10000
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int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
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uint32_t *phy1_con16, uint32_t *phy0_con17,
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uint32_t *phy1_con17)
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{
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unsigned long val = 0;
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int i;
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/*
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* ZQ Calibration:
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* Select Driver Strength,
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* long calibration for manual calibration
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*/
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val = PHY_CON16_RESET_VAL;
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val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
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val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
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val |= ZQ_CLK_DIV_EN;
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writel(val, phy0_con16);
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writel(val, phy1_con16);
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/* Disable termination */
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if (mem->zq_mode_noterm)
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val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
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writel(val, phy0_con16);
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writel(val, phy1_con16);
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/* ZQ_MANUAL_START: Enable */
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val |= ZQ_MANUAL_STR;
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writel(val, phy0_con16);
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writel(val, phy1_con16);
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/* ZQ_MANUAL_START: Disable */
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val &= ~ZQ_MANUAL_STR;
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/*
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* Since we are manaully calibrating the ZQ values,
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* we are looping for the ZQ_init to complete.
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*/
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i = ZQ_INIT_TIMEOUT;
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while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
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sdelay(100);
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i--;
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}
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if (!i)
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return -1;
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writel(val, phy0_con16);
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i = ZQ_INIT_TIMEOUT;
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while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
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sdelay(100);
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i--;
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}
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if (!i)
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return -1;
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writel(val, phy1_con16);
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return 0;
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}
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void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
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{
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unsigned long val;
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if (mode == DDR_MODE_DDR3) {
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val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
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writel(val, phycontrol0);
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}
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/* Update DLL Information: Force DLL Resyncronization */
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val = readl(phycontrol0);
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val |= FP_RSYNC;
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writel(val, phycontrol0);
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/* Reset Force DLL Resyncronization */
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val = readl(phycontrol0);
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val &= ~FP_RSYNC;
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writel(val, phycontrol0);
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}
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void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
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{
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int channel, chip;
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for (channel = 0; channel < mem->dmc_channels; channel++) {
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unsigned long mask;
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mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
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for (chip = 0; chip < mem->chips_to_configure; chip++) {
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int i;
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mask |= chip << DIRECT_CMD_CHIP_SHIFT;
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/* Sending NOP command */
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writel(DIRECT_CMD_NOP | mask, directcmd);
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/*
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* TODO(alim.akhtar@samsung.com): Do we need these
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* delays? This one and the next were not there for
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* DDR3.
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*/
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sdelay(0x10000);
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/* Sending EMRS/MRS commands */
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for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
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writel(mem->direct_cmd_msr[i] | mask,
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directcmd);
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sdelay(0x10000);
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}
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if (mem->send_zq_init) {
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/* Sending ZQINIT command */
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writel(DIRECT_CMD_ZQINIT | mask,
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directcmd);
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sdelay(10000);
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}
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}
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}
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}
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void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
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{
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int channel, chip;
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for (channel = 0; channel < mem->dmc_channels; channel++) {
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unsigned long mask;
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mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
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for (chip = 0; chip < mem->chips_per_channel; chip++) {
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mask |= chip << DIRECT_CMD_CHIP_SHIFT;
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/* PALL (all banks precharge) CMD */
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writel(DIRECT_CMD_PALL | mask, directcmd);
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sdelay(0x10000);
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}
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}
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}
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void mem_ctrl_init(int reset)
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{
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struct spl_machine_param *param = spl_get_machine_params();
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struct mem_timings *mem;
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int ret;
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mem = clock_get_mem_timings();
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/* If there are any other memory variant, add their init call below */
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if (param->mem_type == DDR_MODE_DDR3) {
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ret = ddr3_mem_ctrl_init(mem, reset);
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if (ret) {
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/* will hang if failed to init memory control */
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while (1)
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;
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}
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} else {
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/* will hang if unknow memory type */
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while (1)
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;
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}
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}
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