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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
215 lines
4.9 KiB
C
215 lines
4.9 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* (C) Copyright 2011
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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* Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include <asm/gpio.h>
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#include <linux/byteorder/generic.h>
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#include "fpga.h"
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#ifdef FPGA_DEBUG
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#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
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#else
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#define fpga_debug(fmt, args...)
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#endif
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Altera_CYC2_Passive_Serial_fns altera_fns = {
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fpga_null_fn, /* Altera_pre_fn */
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fpga_config_fn,
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fpga_status_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_null_fn,
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fpga_null_fn,
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};
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Altera_desc cyclone2 = {
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Altera_CYC2,
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fast_passive_parallel,
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Altera_EP3C5_SIZE,
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(void *) &altera_fns,
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NULL,
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0
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};
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#define GPIO_RESET 43
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#define GPIO_DCLK 65
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#define GPIO_nSTATUS 157
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#define GPIO_CONF_DONE 158
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#define GPIO_nCONFIG 159
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#define GPIO_DATA0 54
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#define GPIO_DATA1 55
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#define GPIO_DATA2 56
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#define GPIO_DATA3 57
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#define GPIO_DATA4 58
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#define GPIO_DATA5 60
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#define GPIO_DATA6 61
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#define GPIO_DATA7 62
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DECLARE_GLOBAL_DATA_PTR;
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/* return FPGA_SUCCESS on success, else FPGA_FAIL
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*/
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int mvblx_init_fpga(void)
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{
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fpga_debug("Initializing FPGA interface\n");
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fpga_init();
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fpga_add(fpga_altera, &cyclone2);
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if (gpio_request(GPIO_DCLK, "dclk") ||
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gpio_request(GPIO_nSTATUS, "nStatus") ||
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#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
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gpio_request(GPIO_CONF_DONE, "conf_done") ||
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#endif
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gpio_request(GPIO_nCONFIG, "nConfig") ||
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gpio_request(GPIO_DATA0, "data0") ||
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gpio_request(GPIO_DATA1, "data1") ||
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gpio_request(GPIO_DATA2, "data2") ||
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gpio_request(GPIO_DATA3, "data3") ||
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gpio_request(GPIO_DATA4, "data4") ||
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gpio_request(GPIO_DATA5, "data5") ||
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gpio_request(GPIO_DATA6, "data6") ||
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gpio_request(GPIO_DATA7, "data7")) {
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printf("%s: error requesting GPIOs.", __func__);
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return FPGA_FAIL;
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}
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/* set up outputs */
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gpio_direction_output(GPIO_DCLK, 0);
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gpio_direction_output(GPIO_nCONFIG, 0);
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gpio_direction_output(GPIO_DATA0, 0);
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gpio_direction_output(GPIO_DATA1, 0);
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gpio_direction_output(GPIO_DATA2, 0);
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gpio_direction_output(GPIO_DATA3, 0);
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gpio_direction_output(GPIO_DATA4, 0);
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gpio_direction_output(GPIO_DATA5, 0);
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gpio_direction_output(GPIO_DATA6, 0);
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gpio_direction_output(GPIO_DATA7, 0);
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/* NB omap_free_gpio() resets to an input, so we can't
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* free ie. nCONFIG, or else the FPGA would reset
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* Q: presumably gpio_free() has the same effect?
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*/
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/* set up inputs */
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gpio_direction_input(GPIO_nSTATUS);
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#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
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gpio_direction_input(GPIO_CONF_DONE);
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#endif
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fpga_config_fn(0, 1, 0);
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udelay(60);
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return FPGA_SUCCESS;
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}
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int fpga_null_fn(int cookie)
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{
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return 0;
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}
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int fpga_config_fn(int assert, int flush, int cookie)
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{
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fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
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if (flush) {
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gpio_set_value(GPIO_nCONFIG, !assert);
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udelay(1);
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gpio_set_value(GPIO_nCONFIG, assert);
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}
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return assert;
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}
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int fpga_done_fn(int cookie)
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{
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int result = 0;
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/* since revA of BLX, we will not get this signal. */
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udelay(10);
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#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
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fpga_debug("not waiting for CONF_DONE.");
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result = 1;
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#else
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fpga_debug("CONF_DONE check ... ");
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if (gpio_get_value(GPIO_CONF_DONE)) {
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fpga_debug("high\n");
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result = 1;
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} else
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fpga_debug("low\n");
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gpio_free(GPIO_CONF_DONE);
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#endif
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return result;
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}
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int fpga_status_fn(int cookie)
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{
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int result = 0;
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fpga_debug("STATUS check ... ");
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result = gpio_get_value(GPIO_nSTATUS);
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if (result < 0)
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fpga_debug("error\n");
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else if (result > 0)
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fpga_debug("high\n");
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else
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fpga_debug("low\n");
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return result;
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}
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static inline int _write_fpga(u8 byte)
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{
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gpio_set_value(GPIO_DATA0, byte & 0x01);
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gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
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gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
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gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
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gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
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gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
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gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
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gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
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/* clock */
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gpio_set_value(GPIO_DCLK, 1);
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udelay(1);
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gpio_set_value(GPIO_DCLK, 0);
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udelay(1);
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return 0;
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}
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int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
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{
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unsigned char *data = (unsigned char *) buf;
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int i;
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int headerlen = len - cyclone2.size;
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if (headerlen < 0)
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return FPGA_FAIL;
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else if (headerlen == sizeof(uint32_t)) {
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const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
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char fpgavers_str[fpgavers_len];
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snprintf(fpgavers_str, fpgavers_len, "0x%08x",
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be32_to_cpup((uint32_t*)data));
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setenv("fpgavers", fpgavers_str);
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}
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fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
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for (i = headerlen; i < len; i++)
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_write_fpga(data[i]);
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fpga_debug("-%s\n", __func__);
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return FPGA_SUCCESS;
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}
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