mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
aea02abec5
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
28 lines
683 B
Plaintext
28 lines
683 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_TARGET_THEADORABLE=y
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SPL=y
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CONFIG_FIT=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPL_OF_TRANSLATE=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0xd0012000
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CONFIG_DEBUG_UART_CLOCK=250000000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550=y
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CONFIG_VIDEO_MVEBU=y
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CONFIG_REGEX=y
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CONFIG_LIB_RAND=y
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