mirror of
https://github.com/brain-hackers/u-boot-brain
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9c7dea602e
PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
28 lines
763 B
Makefile
28 lines
763 B
Makefile
#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002
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# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
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obj-y += interrupts.o cpu.o call64.o
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obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
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obj-$(CONFIG_SYS_COREBOOT) += coreboot/
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obj-$(CONFIG_QEMU) += qemu/
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obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
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obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
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obj-$(CONFIG_INTEL_QUARK) += quark/
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obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
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obj-y += irq.o lapic.o
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obj-$(CONFIG_SMP) += mp_init.o
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obj-y += mtrr.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SMP) += sipi_vector.o
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obj-y += turbo.o
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