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![Marek Vasut](/assets/img/avatar_default.png)
Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
752 lines
18 KiB
C
752 lines
18 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <fdtdec.h>
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#include <mmc.h>
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#include <dm.h>
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#include <linux/compat.h>
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#include <linux/dma-direction.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <power/regulator.h>
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#include <asm/unaligned.h>
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#include "matsushita-common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
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{
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return readq(priv->regbase + (reg << 1));
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}
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static void matsu_sd_writeq(struct matsu_sd_priv *priv,
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u64 val, unsigned int reg)
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{
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writeq(val, priv->regbase + (reg << 1));
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}
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static u16 matsu_sd_readw(struct matsu_sd_priv *priv, unsigned int reg)
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{
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return readw(priv->regbase + (reg >> 1));
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}
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static void matsu_sd_writew(struct matsu_sd_priv *priv,
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u16 val, unsigned int reg)
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{
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writew(val, priv->regbase + (reg >> 1));
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}
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static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
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{
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u32 val;
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if (priv->caps & MATSU_SD_CAP_64BIT)
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return readl(priv->regbase + (reg << 1));
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else if (priv->caps & MATSU_SD_CAP_16BIT) {
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val = readw(priv->regbase + (reg >> 1)) & 0xffff;
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if ((reg == MATSU_SD_RSP10) || (reg == MATSU_SD_RSP32) ||
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(reg == MATSU_SD_RSP54) || (reg == MATSU_SD_RSP76)) {
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val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
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}
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return val;
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} else
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return readl(priv->regbase + reg);
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}
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static void matsu_sd_writel(struct matsu_sd_priv *priv,
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u32 val, unsigned int reg)
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{
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if (priv->caps & MATSU_SD_CAP_64BIT)
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writel(val, priv->regbase + (reg << 1));
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if (priv->caps & MATSU_SD_CAP_16BIT) {
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writew(val & 0xffff, priv->regbase + (reg >> 1));
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if (val >> 16)
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writew(val >> 16, priv->regbase + (reg >> 1) + 2);
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} else
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writel(val, priv->regbase + reg);
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}
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static dma_addr_t __dma_map_single(void *ptr, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long addr = (unsigned long)ptr;
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if (dir == DMA_FROM_DEVICE)
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invalidate_dcache_range(addr, addr + size);
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else
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flush_dcache_range(addr, addr + size);
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return addr;
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}
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static void __dma_unmap_single(dma_addr_t addr, size_t size,
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enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE)
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invalidate_dcache_range(addr, addr + size);
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}
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static int matsu_sd_check_error(struct udevice *dev)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
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if (info2 & MATSU_SD_INFO2_ERR_RTO) {
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/*
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* TIMEOUT must be returned for unsupported command. Do not
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* display error log since this might be a part of sequence to
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* distinguish between SD and MMC.
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*/
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return -ETIMEDOUT;
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}
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if (info2 & MATSU_SD_INFO2_ERR_TO) {
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dev_err(dev, "timeout error\n");
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return -ETIMEDOUT;
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}
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if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
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MATSU_SD_INFO2_ERR_IDX)) {
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dev_err(dev, "communication out of sync\n");
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return -EILSEQ;
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}
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if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
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MATSU_SD_INFO2_ERR_ILW)) {
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dev_err(dev, "illegal access\n");
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return -EIO;
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}
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return 0;
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}
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static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
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u32 flag)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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long wait = 1000000;
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int ret;
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while (!(matsu_sd_readl(priv, reg) & flag)) {
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if (wait-- < 0) {
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dev_err(dev, "timeout\n");
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return -ETIMEDOUT;
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}
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ret = matsu_sd_check_error(dev);
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if (ret)
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return ret;
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udelay(1);
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}
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return 0;
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}
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#define matsu_pio_read_fifo(__width, __suffix) \
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static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv, \
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char *pbuf, uint blksz) \
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{ \
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u##__width *buf = (u##__width *)pbuf; \
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int i; \
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\
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if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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*buf++ = matsu_sd_read##__suffix(priv, \
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MATSU_SD_BUF); \
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} \
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} else { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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u##__width data; \
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data = matsu_sd_read##__suffix(priv, \
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MATSU_SD_BUF); \
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put_unaligned(data, buf++); \
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} \
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} \
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}
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matsu_pio_read_fifo(64, q)
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matsu_pio_read_fifo(32, l)
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matsu_pio_read_fifo(16, w)
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static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
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uint blocksize)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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int ret;
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/* wait until the buffer is filled with data */
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ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
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MATSU_SD_INFO2_BRE);
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if (ret)
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return ret;
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/*
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* Clear the status flag _before_ read the buffer out because
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* MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
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*/
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matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
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if (priv->caps & MATSU_SD_CAP_64BIT)
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matsu_pio_read_fifo_64(priv, pbuf, blocksize);
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else if (priv->caps & MATSU_SD_CAP_16BIT)
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matsu_pio_read_fifo_16(priv, pbuf, blocksize);
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else
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matsu_pio_read_fifo_32(priv, pbuf, blocksize);
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return 0;
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}
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#define matsu_pio_write_fifo(__width, __suffix) \
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static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv, \
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const char *pbuf, uint blksz)\
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{ \
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const u##__width *buf = (const u##__width *)pbuf; \
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int i; \
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\
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if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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matsu_sd_write##__suffix(priv, *buf++, \
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MATSU_SD_BUF); \
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} \
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} else { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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u##__width data = get_unaligned(buf++); \
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matsu_sd_write##__suffix(priv, data, \
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MATSU_SD_BUF); \
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} \
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} \
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}
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matsu_pio_write_fifo(64, q)
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matsu_pio_write_fifo(32, l)
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matsu_pio_write_fifo(16, w)
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static int matsu_sd_pio_write_one_block(struct udevice *dev,
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const char *pbuf, uint blocksize)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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int ret;
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/* wait until the buffer becomes empty */
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ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
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MATSU_SD_INFO2_BWE);
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if (ret)
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return ret;
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matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
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if (priv->caps & MATSU_SD_CAP_64BIT)
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matsu_pio_write_fifo_64(priv, pbuf, blocksize);
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else if (priv->caps & MATSU_SD_CAP_16BIT)
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matsu_pio_write_fifo_16(priv, pbuf, blocksize);
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else
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matsu_pio_write_fifo_32(priv, pbuf, blocksize);
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return 0;
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}
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static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
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{
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const char *src = data->src;
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char *dest = data->dest;
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int i, ret;
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for (i = 0; i < data->blocks; i++) {
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if (data->flags & MMC_DATA_READ)
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ret = matsu_sd_pio_read_one_block(dev, dest,
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data->blocksize);
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else
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ret = matsu_sd_pio_write_one_block(dev, src,
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data->blocksize);
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if (ret)
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return ret;
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if (data->flags & MMC_DATA_READ)
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dest += data->blocksize;
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else
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src += data->blocksize;
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}
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return 0;
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}
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static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
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dma_addr_t dma_addr)
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{
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u32 tmp;
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matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
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matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
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/* enable DMA */
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tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
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tmp |= MATSU_SD_EXTMODE_DMA_EN;
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matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
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matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
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/* suppress the warning "right shift count >= width of type" */
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dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
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matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
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matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
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}
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static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
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unsigned int blocks)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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long wait = 1000000 + 10 * blocks;
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while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
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if (wait-- < 0) {
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dev_err(dev, "timeout during DMA\n");
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return -ETIMEDOUT;
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}
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udelay(10);
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}
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if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
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dev_err(dev, "error during DMA\n");
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return -EIO;
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}
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return 0;
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}
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static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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size_t len = data->blocks * data->blocksize;
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void *buf;
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enum dma_data_direction dir;
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dma_addr_t dma_addr;
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u32 poll_flag, tmp;
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int ret;
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tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
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if (data->flags & MMC_DATA_READ) {
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buf = data->dest;
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dir = DMA_FROM_DEVICE;
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poll_flag = MATSU_SD_DMA_INFO1_END_RD2;
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tmp |= MATSU_SD_DMA_MODE_DIR_RD;
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} else {
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buf = (void *)data->src;
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dir = DMA_TO_DEVICE;
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poll_flag = MATSU_SD_DMA_INFO1_END_WR;
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tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
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}
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matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
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dma_addr = __dma_map_single(buf, len, dir);
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matsu_sd_dma_start(priv, dma_addr);
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ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
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__dma_unmap_single(dma_addr, len, dir);
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return ret;
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}
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/* check if the address is DMA'able */
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static bool matsu_sd_addr_is_dmaable(unsigned long addr)
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{
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if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
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return false;
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#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
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defined(CONFIG_SPL_BUILD)
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/*
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* For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
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* of L2, which is unreachable from the DMA engine.
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*/
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if (addr < CONFIG_SPL_STACK)
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return false;
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#endif
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return true;
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}
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int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct matsu_sd_priv *priv = dev_get_priv(dev);
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int ret;
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u32 tmp;
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if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
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dev_err(dev, "command busy\n");
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return -EBUSY;
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}
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/* clear all status flags */
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matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
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matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
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/* disable DMA once */
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tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
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tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
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matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
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matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
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tmp = cmd->cmdidx;
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if (data) {
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matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
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matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
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/* Do not send CMD12 automatically */
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tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
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if (data->blocks > 1)
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tmp |= MATSU_SD_CMD_MULTI;
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if (data->flags & MMC_DATA_READ)
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tmp |= MATSU_SD_CMD_RD;
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}
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/*
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* Do not use the response type auto-detection on this hardware.
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* CMD8, for example, has different response types on SD and eMMC,
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* while this controller always assumes the response type for SD.
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* Set the response type manually.
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*/
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switch (cmd->resp_type) {
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case MMC_RSP_NONE:
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tmp |= MATSU_SD_CMD_RSP_NONE;
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break;
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case MMC_RSP_R1:
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tmp |= MATSU_SD_CMD_RSP_R1;
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break;
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case MMC_RSP_R1b:
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tmp |= MATSU_SD_CMD_RSP_R1B;
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break;
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case MMC_RSP_R2:
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tmp |= MATSU_SD_CMD_RSP_R2;
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break;
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case MMC_RSP_R3:
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tmp |= MATSU_SD_CMD_RSP_R3;
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break;
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default:
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dev_err(dev, "unknown response type\n");
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return -EINVAL;
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}
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dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
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cmd->cmdidx, tmp, cmd->cmdarg);
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matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
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ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
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MATSU_SD_INFO1_RSP);
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if (ret)
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return ret;
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if (cmd->resp_type & MMC_RSP_136) {
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u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
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u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
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u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
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u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
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cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
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((rsp_103_72 & 0xff000000) >> 24);
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cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
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((rsp_71_40 & 0xff000000) >> 24);
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cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
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((rsp_39_8 & 0xff000000) >> 24);
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cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
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} else {
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/* bit 39-8 */
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cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
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}
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if (data) {
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/* use DMA if the HW supports it and the buffer is aligned */
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if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
|
|
matsu_sd_addr_is_dmaable((long)data->src))
|
|
ret = matsu_sd_dma_xfer(dev, data);
|
|
else
|
|
ret = matsu_sd_pio_xfer(dev, data);
|
|
|
|
ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
|
|
MATSU_SD_INFO1_CMP);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
|
|
struct mmc *mmc)
|
|
{
|
|
u32 val, tmp;
|
|
|
|
switch (mmc->bus_width) {
|
|
case 1:
|
|
val = MATSU_SD_OPTION_WIDTH_1;
|
|
break;
|
|
case 4:
|
|
val = MATSU_SD_OPTION_WIDTH_4;
|
|
break;
|
|
case 8:
|
|
val = MATSU_SD_OPTION_WIDTH_8;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
|
|
tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
|
|
tmp |= val;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
|
|
struct mmc *mmc)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
|
|
if (mmc->ddr_mode)
|
|
tmp |= MATSU_SD_IF_MODE_DDR;
|
|
else
|
|
tmp &= ~MATSU_SD_IF_MODE_DDR;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
|
|
}
|
|
|
|
static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
|
|
struct mmc *mmc)
|
|
{
|
|
unsigned int divisor;
|
|
u32 val, tmp;
|
|
|
|
if (!mmc->clock)
|
|
return;
|
|
|
|
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
|
|
|
|
if (divisor <= 1)
|
|
val = MATSU_SD_CLKCTL_DIV1;
|
|
else if (divisor <= 2)
|
|
val = MATSU_SD_CLKCTL_DIV2;
|
|
else if (divisor <= 4)
|
|
val = MATSU_SD_CLKCTL_DIV4;
|
|
else if (divisor <= 8)
|
|
val = MATSU_SD_CLKCTL_DIV8;
|
|
else if (divisor <= 16)
|
|
val = MATSU_SD_CLKCTL_DIV16;
|
|
else if (divisor <= 32)
|
|
val = MATSU_SD_CLKCTL_DIV32;
|
|
else if (divisor <= 64)
|
|
val = MATSU_SD_CLKCTL_DIV64;
|
|
else if (divisor <= 128)
|
|
val = MATSU_SD_CLKCTL_DIV128;
|
|
else if (divisor <= 256)
|
|
val = MATSU_SD_CLKCTL_DIV256;
|
|
else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
|
|
val = MATSU_SD_CLKCTL_DIV512;
|
|
else
|
|
val = MATSU_SD_CLKCTL_DIV1024;
|
|
|
|
tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
|
|
if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
|
|
(tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
|
|
return;
|
|
|
|
/* stop the clock before changing its rate to avoid a glitch signal */
|
|
tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
|
|
|
|
tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
|
|
tmp |= val | MATSU_SD_CLKCTL_OFFEN;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
|
|
|
|
tmp |= MATSU_SD_CLKCTL_SCLKEN;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
|
|
|
|
udelay(1000);
|
|
}
|
|
|
|
int matsu_sd_set_ios(struct udevice *dev)
|
|
{
|
|
struct matsu_sd_priv *priv = dev_get_priv(dev);
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
int ret;
|
|
|
|
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
|
|
mmc->clock, mmc->ddr_mode, mmc->bus_width);
|
|
|
|
ret = matsu_sd_set_bus_width(priv, mmc);
|
|
if (ret)
|
|
return ret;
|
|
matsu_sd_set_ddr_mode(priv, mmc);
|
|
matsu_sd_set_clk_rate(priv, mmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int matsu_sd_get_cd(struct udevice *dev)
|
|
{
|
|
struct matsu_sd_priv *priv = dev_get_priv(dev);
|
|
|
|
if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
|
|
return 1;
|
|
|
|
return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
|
|
MATSU_SD_INFO1_CD);
|
|
}
|
|
|
|
static void matsu_sd_host_init(struct matsu_sd_priv *priv)
|
|
{
|
|
u32 tmp;
|
|
|
|
/* soft reset of the host */
|
|
tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
|
|
tmp &= ~MATSU_SD_SOFT_RST_RSTX;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
|
|
tmp |= MATSU_SD_SOFT_RST_RSTX;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
|
|
|
|
/* FIXME: implement eMMC hw_reset */
|
|
|
|
matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
|
|
|
|
/*
|
|
* Connected to 32bit AXI.
|
|
* This register dropped backward compatibility at version 0x10.
|
|
* Write an appropriate value depending on the IP version.
|
|
*/
|
|
if (priv->version >= 0x10)
|
|
matsu_sd_writel(priv, 0x101, MATSU_SD_HOST_MODE);
|
|
else if (priv->caps & MATSU_SD_CAP_16BIT)
|
|
matsu_sd_writel(priv, 0x1, MATSU_SD_HOST_MODE);
|
|
else
|
|
matsu_sd_writel(priv, 0x0, MATSU_SD_HOST_MODE);
|
|
|
|
if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
|
|
tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
|
|
tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
|
|
matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
|
|
}
|
|
}
|
|
|
|
int matsu_sd_bind(struct udevice *dev)
|
|
{
|
|
struct matsu_sd_plat *plat = dev_get_platdata(dev);
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
int matsu_sd_probe(struct udevice *dev, u32 quirks)
|
|
{
|
|
struct matsu_sd_plat *plat = dev_get_platdata(dev);
|
|
struct matsu_sd_priv *priv = dev_get_priv(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
fdt_addr_t base;
|
|
struct clk clk;
|
|
int ret;
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
struct udevice *vqmmc_dev;
|
|
#endif
|
|
|
|
base = devfdt_get_addr(dev);
|
|
if (base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->regbase = devm_ioremap(dev, base, SZ_2K);
|
|
if (!priv->regbase)
|
|
return -ENOMEM;
|
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
|
|
if (!ret) {
|
|
/* Set the regulator to 3.3V until we support 1.8V modes */
|
|
regulator_set_value(vqmmc_dev, 3300000);
|
|
regulator_set_enable(vqmmc_dev, true);
|
|
}
|
|
#endif
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get host clock\n");
|
|
return ret;
|
|
}
|
|
|
|
/* set to max rate */
|
|
priv->mclk = clk_set_rate(&clk, ULONG_MAX);
|
|
if (IS_ERR_VALUE(priv->mclk)) {
|
|
dev_err(dev, "failed to set rate for host clock\n");
|
|
clk_free(&clk);
|
|
return priv->mclk;
|
|
}
|
|
|
|
ret = clk_enable(&clk);
|
|
clk_free(&clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable host clock\n");
|
|
return ret;
|
|
}
|
|
|
|
plat->cfg.name = dev->name;
|
|
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
|
switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
|
|
1)) {
|
|
case 8:
|
|
plat->cfg.host_caps |= MMC_MODE_8BIT;
|
|
break;
|
|
case 4:
|
|
plat->cfg.host_caps |= MMC_MODE_4BIT;
|
|
break;
|
|
case 1:
|
|
break;
|
|
default:
|
|
dev_err(dev, "Invalid \"bus-width\" value\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (quirks) {
|
|
priv->caps = quirks;
|
|
} else {
|
|
priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
|
|
MATSU_SD_VERSION_IP;
|
|
dev_dbg(dev, "version %x\n", priv->version);
|
|
if (priv->version >= 0x10) {
|
|
priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
|
|
priv->caps |= MATSU_SD_CAP_DIV1024;
|
|
}
|
|
}
|
|
|
|
if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
|
|
NULL))
|
|
priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
|
|
|
|
matsu_sd_host_init(priv);
|
|
|
|
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
plat->cfg.f_min = priv->mclk /
|
|
(priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
|
|
plat->cfg.f_max = priv->mclk;
|
|
plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
|
|
|
|
upriv->mmc = &plat->mmc;
|
|
|
|
return 0;
|
|
}
|