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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6f6b7cfa89
This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
211 lines
5.9 KiB
C
211 lines
5.9 KiB
C
/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on original Kirkwood support which is
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_EDMINIV2_H
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#define _CONFIG_EDMINIV2_H
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/*
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* SPL
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*/
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#define CONFIG_SPL_TEXT_BASE 0xffff0000
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#define CONFIG_SPL_MAX_SIZE 0x0000fff0
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#define CONFIG_SPL_STACK 0x00020000
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#define CONFIG_SPL_BSS_START_ADDR 0x00020000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
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#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
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#define CONFIG_SYS_UBOOT_BASE 0xfff90000
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#define CONFIG_SYS_UBOOT_START 0x00800000
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_MARVELL 1
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#define CONFIG_FEROCEON 1 /* CPU Core subversion */
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#define CONFIG_88F5182 1 /* SOC Name */
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#include <asm/arch/orion5x.h>
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/*
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* CLKs configurations
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*/
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/*
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* Board-specific values for Orion5x MPP low level init:
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* - MPPs 12 to 15 are SATA LEDs (mode 5)
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* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
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* MPP16 to MPP19, mode 0 for others
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*/
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#define ORION5X_MPP0_7 0x00000003
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#define ORION5X_MPP8_15 0x55550000
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#define ORION5X_MPP16_23 0x00005555
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/*
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* Board-specific values for Orion5x GPIO low level init:
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* - GPIO3 is input (RTC interrupt)
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* - GPIO16 is Power LED control (0 = on, 1 = off)
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* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
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* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
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* - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
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* - GPIO22 is SATA disk power status ()
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* - GPIO23 is supply status for SATA disk ()
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* - GPIO24 is supply control for board (write 1 to power off)
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* Last GPIO is 25, further bits are supposed to be 0.
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* Enable mask has ones for INPUT, 0 for OUTPUT.
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* Default is LED ON, board ON :)
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*/
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#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
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#define ORION5X_GPIO_OUT_VALUE 0x00000000
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#define ORION5X_GPIO_IN_POLARITY 0x000000d0
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
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#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
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/*
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* Serial Port configuration
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* The following definitions let you select what serial you want to use
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* for your console driver.
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*/
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
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/*
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* FLASH configuration
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_BASE 0xfff80000
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/* auto boot */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
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#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
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/*
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* Commands configuration
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*/
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/*
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* Network
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
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#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
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#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
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#define CONFIG_PHY_BASE_ADR 0x8
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#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_MII /* expose smi ove miiphy interface */
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#endif
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/*
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* IDE
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*/
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#ifdef CONFIG_IDE
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#define __io
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#define CONFIG_IDE_PREINIT
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/* ED Mini V has an IDE-compatible SATA connector for port 1 */
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#define CONFIG_MVSATA_IDE_USE_PORT1
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/* Needs byte-swapping for ATA data register */
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#define CONFIG_IDE_SWAP_IO
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/* Data, registers and alternate blocks are at the same offset */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
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#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
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/* Each 8-bit ATA register is aligned to a 4-bytes address */
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#define CONFIG_SYS_ATA_STRIDE 4
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/* Controller supports 48-bits LBA addressing */
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#define CONFIG_LBA48
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/* A single bus, a single device */
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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/* ATA registers base is at SATA controller base */
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#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
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/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
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#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
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/* end of IDE defines */
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#endif /* CMD_IDE */
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/*
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* Common USB/EHCI configuration
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*/
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#ifdef CONFIG_CMD_USB
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#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
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#endif /* CONFIG_CMD_USB */
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/*
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* I2C related stuff
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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/*
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* Environment variables configurations
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*/
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#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
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/*
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* Other required minimal configurations
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*/
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#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_LOAD_ADDR 0x00800000
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#define CONFIG_SYS_MEMTEST_START 0x00400000
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#define CONFIG_SYS_MEMTEST_END 0x007fffff
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#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
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/* Enable command line editing */
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/* provide extensive help */
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif /* _CONFIG_EDMINIV2_H */
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