mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 04:49:42 +09:00
f7aa3cd4a8
The E2 Silk port was broken since some time. This patch updates
the E2 Silk port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
NOTE: The port is missing support for I2C1 for DA9063 reset, since the
I2C driver needs to be converted to DM and DT probing. That's not
an issue for this patch though, since the reset was broken on Silk
since forever.
426 lines
9.8 KiB
C
426 lines
9.8 KiB
C
/*
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* board/renesas/silk/silk_spl.c
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <spl.h>
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#define TMU0_MSTP125 BIT(25)
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#define SCIF2_MSTP719 BIT(19)
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#define QSPI_MSTP917 BIT(17)
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#define SD1CKCR 0xE6150078
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#define SD_97500KHZ 0x7
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struct reg_config {
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u16 off;
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u32 val;
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};
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static void dbsc_wait(u16 reg)
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{
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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while (!(readl(dbsc3_0_base + reg) & BIT(0)))
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;
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}
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static void spl_init_sys(void)
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{
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u32 r0 = 0;
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writel(0xa5a5a500, 0xe6020004);
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writel(0xa5a5a500, 0xe6030004);
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asm volatile(
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/* ICIALLU - Invalidate I$ to PoU */
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"mcr 15, 0, %0, cr7, cr5, 0 \n"
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/* BPIALL - Invalidate branch predictors */
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"mcr 15, 0, %0, cr7, cr5, 6 \n"
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/* Set SCTLR[IZ] */
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"mrc 15, 0, %0, cr1, cr0, 0 \n"
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"orr %0, #0x1800 \n"
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"mcr 15, 0, %0, cr1, cr0, 0 \n"
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"isb sy \n"
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:"=r"(r0));
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}
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static void spl_init_pfc(void)
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{
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static const struct reg_config pfc_with_unlock[] = {
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{ 0x0090, 0x00018040 },
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{ 0x0094, 0x00000000 },
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{ 0x0098, 0x00000000 },
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{ 0x0020, 0x94000000 },
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{ 0x0024, 0x00000006 },
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{ 0x0028, 0x40000000 },
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{ 0x002c, 0x00000155 },
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{ 0x0030, 0x00000002 },
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{ 0x0034, 0x00000000 },
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{ 0x0038, 0x00000000 },
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{ 0x003c, 0x00000000 },
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{ 0x0040, 0x60000000 },
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{ 0x0044, 0x36dab6db },
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{ 0x0048, 0x926da012 },
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{ 0x004c, 0x0008c383 },
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{ 0x0050, 0x00000000 },
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{ 0x0054, 0x00000140 },
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{ 0x0004, 0xffffffff },
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{ 0x0008, 0x00ec3fff },
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{ 0x000c, 0x5bffffff },
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{ 0x0010, 0x01bfe1ff },
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{ 0x0014, 0x5bffffff },
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{ 0x0018, 0x0f4b200f },
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{ 0x001c, 0x03ffffff },
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};
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static const struct reg_config pfc_without_unlock[] = {
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{ 0x0100, 0x00000000 },
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{ 0x0104, 0x4203fdf0 },
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{ 0x0108, 0x00000000 },
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{ 0x010c, 0x159007ff },
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{ 0x0110, 0x80000000 },
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{ 0x0114, 0x00de481f },
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{ 0x0118, 0x00000000 },
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};
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static const struct reg_config pfc_with_unlock2[] = {
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{ 0x0060, 0xffffffff },
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{ 0x0064, 0xfffff000 },
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{ 0x0068, 0x55555500 },
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{ 0x006c, 0xffffff00 },
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{ 0x0070, 0x00000000 },
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};
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static const u32 pfc_base = 0xe6060000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
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writel(~pfc_with_unlock[i].val, pfc_base);
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writel(pfc_with_unlock[i].val,
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pfc_base | pfc_with_unlock[i].off);
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}
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for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
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writel(pfc_without_unlock[i].val,
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pfc_base | pfc_without_unlock[i].off);
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
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writel(~pfc_with_unlock2[i].val, pfc_base);
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writel(pfc_with_unlock2[i].val,
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pfc_base | pfc_with_unlock2[i].off);
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}
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}
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static void spl_init_gpio(void)
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{
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static const u16 gpio_offs[] = {
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0x1000, 0x2000, 0x3000, 0x4000
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};
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static const struct reg_config gpio_set[] = {
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{ 0x2000, 0x24000000 },
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{ 0x4000, 0xa4000000 },
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{ 0x5000, 0x0084c000 },
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};
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static const struct reg_config gpio_clr[] = {
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{ 0x1000, 0x01000000 },
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{ 0x2000, 0x24000000 },
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{ 0x3000, 0x00000000 },
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{ 0x4000, 0xa4000000 },
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{ 0x5000, 0x00044380 },
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};
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static const u32 gpio_base = 0xe6050000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x20 | gpio_offs[i]);
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writel(BIT(23), gpio_base | 0x5020);
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x00 | gpio_offs[i]);
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writel(BIT(23), gpio_base | 0x5000);
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for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
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writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
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for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
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writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
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}
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static void spl_init_lbsc(void)
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{
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static const struct reg_config lbsc_config[] = {
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{ 0x00, 0x00000020 },
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{ 0x08, 0x00002020 },
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{ 0x30, 0x2a103320 },
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{ 0x38, 0xff70ff70 },
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};
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static const u16 lbsc_offs[] = {
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0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
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};
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static const u32 lbsc_base = 0xfec00200;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
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writel(lbsc_config[i].val,
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lbsc_base | lbsc_config[i].off);
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writel(lbsc_config[i].val,
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lbsc_base | (lbsc_config[i].off + 4));
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}
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for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
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writel(0, lbsc_base | lbsc_offs[i]);
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}
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static void spl_init_dbsc(void)
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{
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static const struct reg_config dbsc_config1[] = {
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{ 0x0018, 0x21000000 },
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{ 0x0018, 0x11000000 },
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{ 0x0018, 0x10000000 },
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{ 0x0280, 0x0000a55a },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x80000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config2[] = {
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{ 0x0290, 0x00000006 },
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{ 0x02a0, 0x0005c000 },
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};
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static const struct reg_config dbsc_config3r2[] = {
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{ 0x0290, 0x0000000f },
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{ 0x02a0, 0x00181224 },
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};
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static const struct reg_config dbsc_config4[] = {
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{ 0x0290, 0x00000010 },
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{ 0x02a0, 0xf004649b },
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{ 0x0290, 0x00000061 },
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{ 0x02a0, 0x0000006d },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000073 },
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{ 0x0020, 0x00000007 },
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{ 0x0024, 0x0f030a02 },
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{ 0x0030, 0x00000001 },
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{ 0x00b0, 0x00000000 },
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{ 0x0040, 0x00000009 },
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{ 0x0044, 0x00000007 },
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{ 0x0048, 0x00000000 },
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{ 0x0050, 0x00000009 },
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{ 0x0054, 0x000a0009 },
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{ 0x0058, 0x00000021 },
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{ 0x005c, 0x00000018 },
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{ 0x0060, 0x00000005 },
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{ 0x0064, 0x00000020 },
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{ 0x0068, 0x00000007 },
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{ 0x006c, 0x0000000a },
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{ 0x0070, 0x00000009 },
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{ 0x0074, 0x00000010 },
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{ 0x0078, 0x000000ae },
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{ 0x007c, 0x00140005 },
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{ 0x0080, 0x00050004 },
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{ 0x0084, 0x50213005 },
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{ 0x0088, 0x000c0000 },
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{ 0x008c, 0x00000200 },
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{ 0x0090, 0x00000040 },
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{ 0x0100, 0x00000001 },
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{ 0x00c0, 0x00020001 },
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{ 0x00c8, 0x20042004 },
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{ 0x0380, 0x00020003 },
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{ 0x0390, 0x0000001f },
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};
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static const struct reg_config dbsc_config5[] = {
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{ 0x0244, 0x00000011 },
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{ 0x0290, 0x00000003 },
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{ 0x02a0, 0x0300c4e1 },
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{ 0x0290, 0x00000023 },
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{ 0x02a0, 0x00fcb6d0 },
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{ 0x0290, 0x00000011 },
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{ 0x02a0, 0x1000040b },
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{ 0x0290, 0x00000012 },
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{ 0x02a0, 0x85589955 },
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{ 0x0290, 0x00000013 },
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{ 0x02a0, 0x1a852400 },
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{ 0x0290, 0x00000014 },
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{ 0x02a0, 0x300210b4 },
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{ 0x0290, 0x00000015 },
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{ 0x02a0, 0x00000b50 },
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{ 0x0290, 0x00000016 },
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{ 0x02a0, 0x00000006 },
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{ 0x0290, 0x00000017 },
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{ 0x02a0, 0x00000010 },
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{ 0x0290, 0x0000001a },
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{ 0x02a0, 0x910035c7 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config6[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000181 },
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{ 0x0018, 0x11000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config7[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x0000fe01 },
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{ 0x0304, 0x00000000 },
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{ 0x00f4, 0x01004c20 },
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{ 0x00f8, 0x012c00be },
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{ 0x00e0, 0x00000140 },
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{ 0x00e4, 0x00081450 },
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{ 0x00e8, 0x00010000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config8[] = {
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{ 0x0014, 0x00000001 },
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{ 0x0290, 0x00000010 },
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{ 0x02a0, 0xf00464db },
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{ 0x0010, 0x00000001 },
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{ 0x0280, 0x00000000 },
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};
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
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writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
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writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
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for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
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writel(dbsc_config3r2[i].val,
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dbsc3_0_base | dbsc_config3r2[i].off);
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}
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for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
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writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
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dbsc_wait(0x240);
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for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
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writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
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writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
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writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
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writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
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}
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static void spl_init_qspi(void)
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{
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
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static const u32 qspi_base = 0xe6b10000;
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writeb(0x08, qspi_base + 0x00);
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writeb(0x00, qspi_base + 0x01);
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writeb(0x06, qspi_base + 0x02);
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writeb(0x01, qspi_base + 0x0a);
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writeb(0x00, qspi_base + 0x0b);
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writeb(0x00, qspi_base + 0x0c);
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writeb(0x00, qspi_base + 0x0d);
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writeb(0x00, qspi_base + 0x0e);
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writew(0xe080, qspi_base + 0x10);
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writeb(0xc0, qspi_base + 0x18);
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writeb(0x00, qspi_base + 0x18);
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writeb(0x00, qspi_base + 0x08);
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writeb(0x48, qspi_base + 0x00);
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}
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void board_init_f(ulong dummy)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
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/* Set SD1 to the 97.5MHz */
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writel(SD_97500KHZ, SD1CKCR);
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spl_init_sys();
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spl_init_pfc();
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spl_init_gpio();
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spl_init_lbsc();
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spl_init_dbsc();
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spl_init_qspi();
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}
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void spl_board_init(void)
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{
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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const u32 jtag_magic = 0x1337c0de;
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const u32 load_magic = 0xb33fc0de;
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/*
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* If JTAG probe sets special word at 0xe6300020, then it must
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* put U-Boot into RAM and SPL will start it from RAM.
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*/
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if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
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printf("JTAG boot detected!\n");
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while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
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;
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spl_boot_list[0] = BOOT_DEVICE_RAM;
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spl_boot_list[1] = BOOT_DEVICE_NONE;
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return;
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}
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/* Boot from SPI NOR with YMODEM UART fallback. */
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spl_boot_list[0] = BOOT_DEVICE_SPI;
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spl_boot_list[1] = BOOT_DEVICE_UART;
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spl_boot_list[2] = BOOT_DEVICE_NONE;
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}
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void reset_cpu(ulong addr)
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{
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}
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