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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
28 lines
602 B
C
28 lines
602 B
C
/*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_SYSTEM_H
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#define _XTENSA_SYSTEM_H
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#include <asm/arch/core.h>
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#if XCHAL_HAVE_INTERRUPTS
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#define local_irq_save(flags) \
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__asm__ __volatile__ ("rsil %0, %1" \
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: "=a"(flags) \
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: "I"(XCHAL_EXCM_LEVEL) \
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: "memory")
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#define local_irq_restore(flags) \
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__asm__ __volatile__ ("wsr %0, ps\n\t" \
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"rsync" \
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:: "a"(flags) : "memory")
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#else
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#define local_irq_save(flags) ((void)(flags))
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#define local_irq_restore(flags) ((void)(flags))
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#endif
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#endif
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