mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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/* Assert or de-assert SoCFPGA reset manager reset. */
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void socfpga_per_reset(u32 reset, int set)
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{
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const u32 *reg;
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u32 rstmgr_bank = RSTMGR_BANK(reset);
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switch (rstmgr_bank) {
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case 0:
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reg = &reset_manager_base->mpu_mod_reset;
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break;
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case 1:
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reg = &reset_manager_base->per_mod_reset;
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break;
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case 2:
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reg = &reset_manager_base->per2_mod_reset;
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break;
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case 3:
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reg = &reset_manager_base->brg_mod_reset;
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break;
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case 4:
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reg = &reset_manager_base->misc_mod_reset;
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break;
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default:
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return;
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}
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if (set)
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setbits_le32(reg, 1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
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writel(~l4wd0, &reset_manager_base->per_mod_reset);
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writel(0xffffffff, &reset_manager_base->per2_mod_reset);
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}
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/*
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* Release peripherals from reset based on handoff
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*/
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void reset_deassert_peripherals_handoff(void)
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{
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writel(0, &reset_manager_base->per_mod_reset);
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}
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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void socfpga_bridges_reset(int enable)
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{
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/* For SoCFPGA-VT, this is NOP. */
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return;
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}
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#else
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#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
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#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
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#define L3REGS_REMAP_OCRAM_MASK 0x01
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void socfpga_bridges_reset(int enable)
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{
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const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
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L3REGS_REMAP_HPS2FPGA_MASK |
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L3REGS_REMAP_OCRAM_MASK;
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if (enable) {
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/* brdmodrst */
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writel(0xffffffff, &reset_manager_base->brg_mod_reset);
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} else {
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writel(0, &sysmgr_regs->iswgrp_handoff[0]);
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writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
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/* Check signal from FPGA. */
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if (!fpgamgr_test_fpga_ready()) {
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/* FPGA not ready, do nothing. We allow system to boot
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* without FPGA ready. So, return 0 instead of error. */
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printf("%s: FPGA not ready, aborting.\n", __func__);
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return;
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}
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/* brdmodrst */
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writel(0, &reset_manager_base->brg_mod_reset);
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/* Remap the bridges into memory map */
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writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
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}
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return;
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}
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#endif
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