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https://github.com/brain-hackers/u-boot-brain
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c8a6bc9683
This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
100 lines
2.0 KiB
C
100 lines
2.0 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CRU_RK3399_H_
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#define __ASM_ARCH_CRU_RK3399_H_
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#include <common.h>
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3399_clk_priv {
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struct rk3399_cru *cru;
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ulong rate;
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};
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struct rk3399_pmucru {
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u32 ppll_con[6];
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u32 reserved[0x1a];
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u32 pmucru_clksel[6];
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u32 pmucru_clkfrac_con[2];
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u32 reserved2[0x18];
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u32 pmucru_clkgate_con[3];
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u32 reserved3;
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u32 pmucru_softrst_con[2];
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u32 reserved4[2];
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u32 pmucru_rstnhold_con[2];
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u32 reserved5[2];
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u32 pmucru_gatedis_con[2];
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};
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check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
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struct rk3399_cru {
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u32 apll_l_con[6];
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u32 reserved[2];
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u32 apll_b_con[6];
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u32 reserved1[2];
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u32 dpll_con[6];
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u32 reserved2[2];
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u32 cpll_con[6];
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u32 reserved3[2];
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u32 gpll_con[6];
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u32 reserved4[2];
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u32 npll_con[6];
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u32 reserved5[2];
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u32 vpll_con[6];
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u32 reserved6[0x0a];
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u32 clksel_con[108];
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u32 reserved7[0x14];
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u32 clkgate_con[35];
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u32 reserved8[0x1d];
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u32 softrst_con[21];
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u32 reserved9[0x2b];
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u32 glb_srst_fst_value;
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u32 glb_srst_snd_value;
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u32 glb_cnt_th;
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u32 misc_con;
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u32 glb_rst_con;
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u32 glb_rst_st;
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u32 reserved10[0x1a];
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u32 sdmmc_con[2];
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u32 sdio0_con[2];
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u32 sdio1_con[2];
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};
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check_member(rk3399_cru, sdio1_con[1], 0x594);
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24*MHz)
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#define APLL_HZ (600*MHz)
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#define GPLL_HZ (594*MHz)
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#define CPLL_HZ (384*MHz)
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#define PPLL_HZ (676*MHz)
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#define PMU_PCLK_HZ (48*MHz)
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#define ACLKM_CORE_HZ (300*MHz)
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#define ATCLK_CORE_HZ (300*MHz)
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#define PCLK_DBG_HZ (100*MHz)
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#define PERIHP_ACLK_HZ (148500*KHz)
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#define PERIHP_HCLK_HZ (148500*KHz)
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#define PERIHP_PCLK_HZ (37125*KHz)
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#define PERILP0_ACLK_HZ (99000*KHz)
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#define PERILP0_HCLK_HZ (99000*KHz)
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#define PERILP0_PCLK_HZ (49500*KHz)
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#define PERILP1_HCLK_HZ (99000*KHz)
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#define PERILP1_PCLK_HZ (49500*KHz)
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#define PWM_CLOCK_HZ PMU_PCLK_HZ
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enum apll_l_frequencies {
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APLL_L_1600_MHZ,
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APLL_L_600_MHZ,
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};
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#endif /* __ASM_ARCH_CRU_RK3399_H_ */
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