mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
![Patrick Delaunay](/assets/img/avatar_default.png)
Since commit d877f8fd0f
("arm: provide a function for boards init
code to modify MMU virtual-physical map") the parameter of
mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE
aligned.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
627 lines
15 KiB
C
627 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <env.h>
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#include <init.h>
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#include <log.h>
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#include <misc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/bsec.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <linux/bitops.h>
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/* RCC register */
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#define RCC_TZCR (STM32_RCC_BASE + 0x00)
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#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
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#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
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#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
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#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
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#define RCC_BDCR_VSWRST BIT(31)
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#define RCC_BDCR_RTCSRC GENMASK(17, 16)
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#define RCC_DBGCFGR_DBGCKEN BIT(8)
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/* Security register */
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#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
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#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
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#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
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#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
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#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
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#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
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#define PWR_CR1 (STM32_PWR_BASE + 0x00)
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#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
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#define PWR_CR1_DBP BIT(8)
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#define PWR_MCUCR_SBF BIT(6)
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/* DBGMCU register */
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#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
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#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
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#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define DBGMCU_IDC_DEV_ID_SHIFT 0
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#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
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#define DBGMCU_IDC_REV_ID_SHIFT 16
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/* GPIOZ registers */
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#define GPIOZ_SECCFGR 0x54004030
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/* boot interface from Bootrom
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* - boot instance = bit 31:16
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* - boot device = bit 15:0
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*/
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#define BOOTROM_PARAM_ADDR 0x2FFC0078
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#define BOOTROM_MODE_MASK GENMASK(15, 0)
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#define BOOTROM_MODE_SHIFT 0
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#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
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#define BOOTROM_INSTANCE_SHIFT 16
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/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(7, 0)
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/* Package = bit 27:29 of OTP16
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* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
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* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
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* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
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* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
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* - others: Reserved
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*/
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#define PKG_SHIFT 27
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#define PKG_MASK GENMASK(2, 0)
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/*
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* early TLB into the .data section so that it not get cleared
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* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
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*/
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u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#ifndef CONFIG_TFABOOT
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static void security_init(void)
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{
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/* Disable the backup domain write protection */
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/* the protection is enable at each reset by hardware */
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/* And must be disable by software */
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setbits_le32(PWR_CR1, PWR_CR1_DBP);
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while (!(readl(PWR_CR1) & PWR_CR1_DBP))
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;
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/* If RTC clock isn't enable so this is a cold boot then we need
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* to reset the backup domain
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*/
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if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
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setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
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;
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clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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}
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/* allow non secure access in Write/Read for all peripheral */
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writel(GENMASK(25, 0), ETZPC_DECPROT0);
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/* Open SYSRAM for no secure access */
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writel(0x0, ETZPC_TZMA1_SIZE);
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/* enable TZC1 TZC2 clock */
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writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
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/* Region 0 set to no access by default */
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/* bit 0 / 16 => nsaid0 read/write Enable
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* bit 1 / 17 => nsaid1 read/write Enable
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* ...
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* bit 15 / 31 => nsaid15 read/write Enable
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*/
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writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
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/* bit 30 / 31 => Secure Global Enable : write/read */
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/* bit 0 / 1 => Region Enable for filter 0/1 */
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writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
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/* Enable Filter 0 and 1 */
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setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
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/* RCC trust zone deactivated */
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writel(0x0, RCC_TZCR);
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/* TAMP: deactivate the internal tamper
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* Bit 23 ITAMP8E: monotonic counter overflow
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* Bit 20 ITAMP5E: RTC calendar overflow
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* Bit 19 ITAMP4E: HSE monitoring
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* Bit 18 ITAMP3E: LSE monitoring
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* Bit 16 ITAMP1E: RTC power domain supply monitoring
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*/
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writel(0x0, TAMP_CR1);
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/* GPIOZ: deactivate the security */
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writel(BIT(0), RCC_MP_AHB5ENSETR);
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writel(0x0, GPIOZ_SECCFGR);
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}
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#endif /* CONFIG_TFABOOT */
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/*
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* Debug init
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*/
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static void dbgmcu_init(void)
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{
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/*
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* Freeze IWDG2 if Cortex-A7 is in debug mode
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* done in TF-A for TRUSTED boot and
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* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
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*/
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if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
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}
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}
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void spl_board_init(void)
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{
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dbgmcu_init();
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}
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#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
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#if !defined(CONFIG_TFABOOT) && \
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(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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/* get bootmode from ROM code boot context: saved in TAMP register */
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static void update_bootmode(void)
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{
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u32 boot_mode;
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u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
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u32 bootrom_device, bootrom_instance;
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/* enable TAMP clock = RTCAPBEN */
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writel(BIT(8), RCC_MP_APB5ENSETR);
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/* read bootrom context */
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bootrom_device =
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(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
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bootrom_instance =
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(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
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boot_mode =
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((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
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((bootrom_instance << BOOT_INSTANCE_SHIFT) &
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BOOT_INSTANCE_MASK);
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/* save the boot mode in TAMP backup register */
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_MODE_MASK,
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boot_mode << TAMP_BOOT_MODE_SHIFT);
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}
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#endif
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u32 get_bootmode(void)
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{
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/* read bootmode from TAMP backup register */
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return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
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TAMP_BOOT_MODE_SHIFT;
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}
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/*
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* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
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* MMU/TLB is updated in enable_caches() for U-Boot after relocation
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* or is deactivated in U-Boot entry function start.S::cpu_init_cp15
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*/
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static void early_enable_caches(void)
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{
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/* I-cache is already enabled in start.S: cpu_init_cp15 */
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if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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return;
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gd->arch.tlb_size = PGTABLE_SIZE;
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gd->arch.tlb_addr = (unsigned long)&early_tlb;
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dcache_enable();
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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mmu_set_region_dcache_behaviour(
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ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
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round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
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DCACHE_DEFAULT_OPTION);
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else
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
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DCACHE_DEFAULT_OPTION);
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}
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/*
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* Early system init
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*/
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int arch_cpu_init(void)
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{
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u32 boot_mode;
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early_enable_caches();
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/* early armv7 timer init: needed for polling */
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timer_init();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#ifndef CONFIG_TFABOOT
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security_init();
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update_bootmode();
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#endif
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/* Reset Coprocessor state unless it wakes up from Standby power mode */
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if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
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writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
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writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
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}
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#endif
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boot_mode = get_bootmode();
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if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
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#if defined(CONFIG_DEBUG_UART) && \
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!defined(CONFIG_TFABOOT) && \
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(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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else
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debug_uart_init();
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#endif
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return 0;
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}
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void enable_caches(void)
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{
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/* I-cache is already enabled in start.S: icache_enable() not needed */
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/* deactivate the data cache, early enabled in arch_cpu_init() */
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dcache_disable();
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/*
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* update MMU after relocation and enable the data cache
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* warning: the TLB location udpated in board_f.c::reserve_mmu
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*/
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dcache_enable();
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}
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static u32 read_idc(void)
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{
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/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
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if (bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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return readl(DBGMCU_IDC);
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}
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if (CONFIG_IS_ENABLED(STM32MP15x))
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return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
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else
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return 0x0;
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}
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u32 get_cpu_dev(void)
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{
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return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
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}
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u32 get_cpu_rev(void)
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{
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return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
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}
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static u32 get_otp(int index, int shift, int mask)
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{
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int ret;
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struct udevice *dev;
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u32 otp = 0;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (!ret)
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ret = misc_read(dev, STM32_BSEC_SHADOW(index),
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&otp, sizeof(otp));
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return (otp >> shift) & mask;
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}
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/* Get Device Part Number (RPN) from OTP */
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static u32 get_cpu_rpn(void)
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{
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return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
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}
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u32 get_cpu_type(void)
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{
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return (get_cpu_dev() << 16) | get_cpu_rpn();
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}
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/* Get Package options from OTP */
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u32 get_cpu_package(void)
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{
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return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
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}
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void get_soc_name(char name[SOC_NAME_SIZE])
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{
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char *cpu_s, *cpu_r, *pkg;
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/* MPUs Part Numbers */
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switch (get_cpu_type()) {
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case CPU_STM32MP157Fxx:
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cpu_s = "157F";
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break;
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case CPU_STM32MP157Dxx:
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cpu_s = "157D";
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break;
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case CPU_STM32MP157Cxx:
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cpu_s = "157C";
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break;
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case CPU_STM32MP157Axx:
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cpu_s = "157A";
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break;
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case CPU_STM32MP153Fxx:
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cpu_s = "153F";
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break;
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case CPU_STM32MP153Dxx:
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cpu_s = "153D";
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break;
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case CPU_STM32MP153Cxx:
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cpu_s = "153C";
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break;
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case CPU_STM32MP153Axx:
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cpu_s = "153A";
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break;
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case CPU_STM32MP151Fxx:
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cpu_s = "151F";
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break;
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case CPU_STM32MP151Dxx:
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cpu_s = "151D";
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break;
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case CPU_STM32MP151Cxx:
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cpu_s = "151C";
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break;
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case CPU_STM32MP151Axx:
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cpu_s = "151A";
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break;
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default:
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cpu_s = "????";
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break;
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}
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/* Package */
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switch (get_cpu_package()) {
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case PKG_AA_LBGA448:
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pkg = "AA";
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break;
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case PKG_AB_LBGA354:
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pkg = "AB";
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break;
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case PKG_AC_TFBGA361:
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pkg = "AC";
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break;
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case PKG_AD_TFBGA257:
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pkg = "AD";
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break;
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default:
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pkg = "??";
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break;
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}
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/* REVISION */
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switch (get_cpu_rev()) {
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case CPU_REVA:
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cpu_r = "A";
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break;
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case CPU_REVB:
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cpu_r = "B";
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break;
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case CPU_REVZ:
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cpu_r = "Z";
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break;
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default:
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cpu_r = "?";
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break;
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}
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char name[SOC_NAME_SIZE];
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get_soc_name(name);
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printf("CPU: %s\n", name);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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static void setup_boot_mode(void)
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{
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const u32 serial_addr[] = {
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STM32_USART1_BASE,
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STM32_USART2_BASE,
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STM32_USART3_BASE,
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STM32_UART4_BASE,
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STM32_UART5_BASE,
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STM32_USART6_BASE,
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STM32_UART7_BASE,
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STM32_UART8_BASE
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};
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char cmd[60];
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u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
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u32 boot_mode =
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(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
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unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
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u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
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struct udevice *dev;
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int alias;
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pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
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__func__, boot_ctx, boot_mode, instance, forced_mode);
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switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
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case BOOT_SERIAL_UART:
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if (instance > ARRAY_SIZE(serial_addr))
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break;
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/* serial : search associated alias in devicetree */
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sprintf(cmd, "serial@%x", serial_addr[instance]);
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if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
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break;
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if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
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dev_of_offset(dev), &alias))
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break;
|
|
sprintf(cmd, "%d", alias);
|
|
env_set("boot_device", "serial");
|
|
env_set("boot_instance", cmd);
|
|
|
|
/* restore console on uart when not used */
|
|
if (gd->cur_serial_dev != dev) {
|
|
gd->flags &= ~(GD_FLG_SILENT |
|
|
GD_FLG_DISABLE_CONSOLE);
|
|
printf("serial boot with console enabled!\n");
|
|
}
|
|
break;
|
|
case BOOT_SERIAL_USB:
|
|
env_set("boot_device", "usb");
|
|
env_set("boot_instance", "0");
|
|
break;
|
|
case BOOT_FLASH_SD:
|
|
case BOOT_FLASH_EMMC:
|
|
sprintf(cmd, "%d", instance);
|
|
env_set("boot_device", "mmc");
|
|
env_set("boot_instance", cmd);
|
|
break;
|
|
case BOOT_FLASH_NAND:
|
|
env_set("boot_device", "nand");
|
|
env_set("boot_instance", "0");
|
|
break;
|
|
case BOOT_FLASH_SPINAND:
|
|
env_set("boot_device", "spi-nand");
|
|
env_set("boot_instance", "0");
|
|
break;
|
|
case BOOT_FLASH_NOR:
|
|
env_set("boot_device", "nor");
|
|
env_set("boot_instance", "0");
|
|
break;
|
|
default:
|
|
pr_debug("unexpected boot mode = %x\n", boot_mode);
|
|
break;
|
|
}
|
|
|
|
switch (forced_mode) {
|
|
case BOOT_FASTBOOT:
|
|
printf("Enter fastboot!\n");
|
|
env_set("preboot", "env set preboot; fastboot 0");
|
|
break;
|
|
case BOOT_STM32PROG:
|
|
env_set("boot_device", "usb");
|
|
env_set("boot_instance", "0");
|
|
break;
|
|
case BOOT_UMS_MMC0:
|
|
case BOOT_UMS_MMC1:
|
|
case BOOT_UMS_MMC2:
|
|
printf("Enter UMS!\n");
|
|
instance = forced_mode - BOOT_UMS_MMC0;
|
|
sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
|
|
env_set("preboot", cmd);
|
|
break;
|
|
case BOOT_RECOVERY:
|
|
env_set("preboot", "env set preboot; run altbootcmd");
|
|
break;
|
|
case BOOT_NORMAL:
|
|
break;
|
|
default:
|
|
pr_debug("unexpected forced boot mode = %x\n", forced_mode);
|
|
break;
|
|
}
|
|
|
|
/* clear TAMP for next reboot */
|
|
clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
|
|
}
|
|
|
|
/*
|
|
* If there is no MAC address in the environment, then it will be initialized
|
|
* (silently) from the value in the OTP.
|
|
*/
|
|
__weak int setup_mac_address(void)
|
|
{
|
|
#if defined(CONFIG_NET)
|
|
int ret;
|
|
int i;
|
|
u32 otp[2];
|
|
uchar enetaddr[6];
|
|
struct udevice *dev;
|
|
|
|
/* MAC already in environment */
|
|
if (eth_env_get_enetaddr("ethaddr", enetaddr))
|
|
return 0;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
|
DM_GET_DRIVER(stm32mp_bsec),
|
|
&dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
|
|
otp, sizeof(otp));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
enetaddr[i] = ((uint8_t *)&otp)[i];
|
|
|
|
if (!is_valid_ethaddr(enetaddr)) {
|
|
pr_err("invalid MAC address in OTP %pM\n", enetaddr);
|
|
return -EINVAL;
|
|
}
|
|
pr_debug("OTP MAC address = %pM\n", enetaddr);
|
|
ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
|
|
if (!ret)
|
|
pr_err("Failed to set mac address %pM from OTP: %d\n",
|
|
enetaddr, ret);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int setup_serial_number(void)
|
|
{
|
|
char serial_string[25];
|
|
u32 otp[3] = {0, 0, 0 };
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
if (env_get("serial#"))
|
|
return 0;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
|
DM_GET_DRIVER(stm32mp_bsec),
|
|
&dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
|
|
otp, sizeof(otp));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
|
|
env_set("serial#", serial_string);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int arch_misc_init(void)
|
|
{
|
|
setup_boot_mode();
|
|
setup_mac_address();
|
|
setup_serial_number();
|
|
|
|
return 0;
|
|
}
|