mirror of
https://github.com/brain-hackers/u-boot-brain
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37648b600c
The dart6ul has an i2c eeprom at 0x50 which contains, among other things, the manufacturing/revision/options info of the SoM. This patch replaces the current checkboard() implementation with a more exhaustive one based on the content of the eeprom. Since this code uses the new driver model, some changes were also required in the DTS to make the nodes related to i2c available before relocation. This code was inspired from the supported u-boot code from Variscite which can be found here: https://github.com/varigit/uboot-imx/tree/imx_v2018.03_4.14.78_1.0.0_ga_var02 New output example: Board: PN: VSM-6UL-705B, Assy: AS1812142257, Date: 2019 Feb 17 Storage: eMMC, Wifi: yes, DDR: 1024 MiB, Rev: 2.4G Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com>
333 lines
9.5 KiB
C
333 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2019 Variscite Ltd.
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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*/
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#include <init.h>
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#include <net.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <dm.h>
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#include <fsl_esdhc_imx.h>
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#include <i2c_eeprom.h>
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#include <linux/bitops.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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clrbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/*
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* config gpmi and bch clock to 100 MHz
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* bch/gpmi select PLL2 PFD2 400M
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* 100M = 400M / 4
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*/
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clrbits_le32(&mxc_ccm->cscmr1,
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MXC_CCM_CSCMR1_BCH_CLK_SEL |
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MXC_CCM_CSCMR1_GPMI_CLK_SEL);
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clrsetbits_le32(&mxc_ccm->cscdr1,
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MXC_CCM_CSCDR1_BCH_PODF_MASK |
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MXC_CCM_CSCDR1_GPMI_PODF_MASK,
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(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
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(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
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PAD_CTL_ODE)
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/*
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* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
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* be used for ENET1 or ENET2, cannot be used for both.
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*/
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec2_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_fec(int fec_id)
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{
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if (fec_id == 0)
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imx_iomux_v3_setup_multiple_pads(fec1_pads,
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ARRAY_SIZE(fec1_pads));
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else
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imx_iomux_v3_setup_multiple_pads(fec2_pads,
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ARRAY_SIZE(fec2_pads));
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}
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int board_eth_init(struct bd_info *bis)
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{
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int ret = 0;
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ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
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/* USB Ethernet Gadget */
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usb_eth_initialize(bis);
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#endif
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return ret;
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}
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static int setup_fec(int fec_id)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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if (fec_id == 0) {
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/*
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* Use 50M anatop loopback REF_CLK1 for ENET1,
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* clear gpr1[13], set gpr1[17].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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} else {
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/*
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* Use 50M anatop loopback REF_CLK2 for ENET2,
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* clear gpr1[14], set gpr1[18].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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}
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ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
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if (ret)
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return ret;
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enable_enet_clk(1);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
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* 50 MHz RMII clock mode.
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif /* CONFIG_FEC_MXC */
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int board_early_init_f(void)
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{
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setup_iomux_fec(CONFIG_FEC_ENET_DEV);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_FEC_MXC
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setup_fec(CONFIG_FEC_ENET_DEV);
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#endif
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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/* length of strings stored in the eeprom */
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#define DART6UL_PN_LEN 16
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#define DART6UL_ASSY_LEN 16
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#define DART6UL_DATE_LEN 12
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/* eeprom content, 512 bytes */
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struct dart6ul_info {
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u32 magic;
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u8 partnumber[DART6UL_PN_LEN];
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u8 assy[DART6UL_ASSY_LEN];
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u8 date[DART6UL_DATE_LEN];
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u32 custom_addr_val[32];
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struct cmd {
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u8 addr;
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u8 index;
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} custom_cmd[150];
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u8 res[33];
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u8 som_info;
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u8 ddr_size;
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u8 crc;
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} __attribute__ ((__packed__));
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#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
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#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1)
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#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3)
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#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8)
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#define DART6UL_INFO_MAGIC 0x32524156
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static const char *som_info_storage_to_str(u8 som_info)
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{
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switch (DART6UL_INFO_STORAGE_GET(som_info)) {
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case 0x0: return "none (SD only)";
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case 0x1: return "NAND";
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case 0x2: return "eMMC";
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default: return "unknown";
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}
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}
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static const char *som_info_rev_to_str(u8 som_info)
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{
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switch (DART6UL_INFO_REV_GET(som_info)) {
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case 0x0: return "2.4G";
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case 0x1: return "5G";
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default: return "unknown";
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}
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}
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int checkboard(void)
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{
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const char *path = "eeprom0";
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struct dart6ul_info *info;
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struct udevice *dev;
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int ret, off;
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off = fdt_path_offset(gd->fdt_blob, path);
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if (off < 0) {
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printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
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return off;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
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if (ret) {
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printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
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return ret;
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}
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info = malloc(sizeof(struct dart6ul_info));
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if (!info)
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return -ENOMEM;
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ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
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sizeof(struct dart6ul_info));
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if (ret) {
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printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
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free(info);
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return ret;
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}
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if (info->magic != DART6UL_INFO_MAGIC) {
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printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
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info->magic, DART6UL_INFO_MAGIC);
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/* do not fail if the content is invalid */
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free(info);
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return 0;
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}
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/* make sure strings are null terminated */
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info->partnumber[DART6UL_PN_LEN - 1] = '\0';
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info->assy[DART6UL_ASSY_LEN - 1] = '\0';
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info->date[DART6UL_DATE_LEN - 1] = '\0';
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printf("Board: PN: %s, Assy: %s, Date: %s\n"
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" Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
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info->partnumber,
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info->assy,
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info->date,
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som_info_storage_to_str(info->som_info),
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DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
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DART6UL_DDRSIZE_IN_MIB(info->ddr_size),
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som_info_rev_to_str(info->som_info));
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free(info);
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return 0;
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}
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