mirror of
https://github.com/brain-hackers/u-boot-brain
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b80a660338
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.
Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.
This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.
Signed-off-by: Pekon Gupta <pekon@ti.com>
334 lines
9.9 KiB
C
334 lines
9.9 KiB
C
/*
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* (C) Copyright 2011 Logic Product Development <www.logicpd.com>
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* Peter Barada <peter.barada@logicpd.com>
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*
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* Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
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* reference boards.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP /* in a TI OMAP core */
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#define CONFIG_OMAP34XX /* which is a 34XX */
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#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
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#define CONFIG_OMAP_GPIO
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#define CONFIG_OMAP_COMMON
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#define CONFIG_SYS_TEXT_BASE 0x80400000
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_DOS_PARTITION
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
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"1920k(u-boot),128k(u-boot-env),"\
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"4m(kernel),-(fs)"
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_SYS_NO_FLASH
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_OMAP34XX
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_POWER
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_QUIET_TEST
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
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/* partition */
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/* Environment information */
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#define CONFIG_BOOTDELAY 2
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/*
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* PREBOOT assumes the 4.3" display is attached. User can interrupt
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* and modify display variable to suit their needs.
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*/
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#define CONFIG_PREBOOT \
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"echo ======================NOTICE============================;"\
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"echo \"The u-boot environment is not set.\";" \
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"echo \"If using a display a valid display varible for your panel\";" \
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"echo \"needs to be set.\";" \
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"echo \"Valid display options are:\";" \
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"echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
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"echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
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"echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
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"echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
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"echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
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"echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
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"echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
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"echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
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"echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
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"echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
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"setenv display 15;" \
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"setenv preboot;" \
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"saveenv;"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81000000\0" \
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"bootfile=uImage\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"mmcdev=0\0" \
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"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"run defaultboot;" \
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"fi; " \
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"else run defaultboot; fi\0" \
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"defaultboot=run mmcramboot\0" \
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"consoledevice=ttyO0\0" \
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"display=15\0" \
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"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
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"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
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"rotation=0\0" \
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"vrfb_arg=if itest ${rotation} -ne 0; then " \
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"setenv bootargs ${bootargs} omapfb.vrfb=y " \
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"omapfb.rotate=${rotation}; " \
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"fi\0" \
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"otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
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"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
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"${otherbootargs};" \
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"run addmtdparts; " \
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"run vrfb_arg\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo 'Running bootscript from mmc ...'; " \
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"source ${loadaddr}\0" \
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"loaduimage=mmc rescan ${mmcdev}; " \
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"fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
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"ramdisksize=64000\0" \
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"ramdiskaddr=0x82000000\0" \
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"ramdiskimage=rootfs.ext2.gz.uboot\0" \
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"ramargs=run setconsole; setenv bootargs console=${console} " \
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"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
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"mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
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"run ramargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"run loaduimage; " \
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"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
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"bootm ${loadaddr} ${ramdiskaddr}\0" \
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"ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
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"run ramargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"tftpboot ${loadaddr} ${bootfile}; "\
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"tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
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"bootm ${loadaddr} ${ramdiskaddr}\0"
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#define CONFIG_BOOTCOMMAND \
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"run autoboot"
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#define CONFIG_AUTO_COMPLETE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "OMAP Logic # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#elif defined(CONFIG_CMD_ONENAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#endif
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* SMSC922x Ethernet
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*/
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_SMC911X_BASE 0x08000000
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#endif /* (CONFIG_CMD_NET) */
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/*
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* BOOTP fields
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*/
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#define CONFIG_BOOTP_SUBNETMASK 0x00000001
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#define CONFIG_BOOTP_GATEWAY 0x00000002
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#define CONFIG_BOOTP_HOSTNAME 0x00000004
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#define CONFIG_BOOTP_BOOTPATH 0x00000010
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#endif /* __CONFIG_H */
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