mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 10:58:52 +09:00
![Joe Hershberger](/assets/img/avatar_default.png)
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
657 lines
17 KiB
C
657 lines
17 KiB
C
/*
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* Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011 PetaLogix
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* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#if !defined(CONFIG_PHYLIB)
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# error AXI_ETHERNET requires PHYLIB
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#endif
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/* Link setup */
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#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
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#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
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#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
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#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
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/* Interrupt Status/Enable/Mask Registers bit definitions */
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#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
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#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
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/* Receive Configuration Word 1 (RCW1) Register bit definitions */
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#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
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/* Transmitter Configuration (TC) Register bit definitions */
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#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
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#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
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/* MDIO Management Configuration (MC) Register bit definitions */
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#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
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/* MDIO Management Control Register (MCR) Register bit definitions */
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#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
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#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
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#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
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#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
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#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
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#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
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#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
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#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
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#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
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/* DMA macros */
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/* Bitmasks of XAXIDMA_CR_OFFSET register */
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#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
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#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
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/* Bitmasks of XAXIDMA_SR_OFFSET register */
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#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
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/* Bitmask for interrupts */
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#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
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#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
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#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
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/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
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#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
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#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
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#define DMAALIGN 128
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static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
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/* Reflect dma offsets */
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struct axidma_reg {
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u32 control; /* DMACR */
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u32 status; /* DMASR */
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u32 current; /* CURDESC */
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u32 reserved;
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u32 tail; /* TAILDESC */
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};
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/* Private driver structures */
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struct axidma_priv {
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struct axidma_reg *dmatx;
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struct axidma_reg *dmarx;
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int phyaddr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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/* BD descriptors */
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struct axidma_bd {
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u32 next; /* Next descriptor pointer */
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u32 reserved1;
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u32 phys; /* Buffer address */
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u32 reserved2;
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u32 reserved3;
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u32 reserved4;
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u32 cntrl; /* Control */
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u32 status; /* Status */
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u32 app0;
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u32 app1; /* TX start << 16 | insert */
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u32 app2; /* TX csum seed */
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u32 app3;
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u32 app4;
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u32 sw_id_offset;
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u32 reserved5;
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u32 reserved6;
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};
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/* Static BDs - driver uses only one BD */
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static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
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static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
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struct axi_regs {
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u32 reserved[3];
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u32 is; /* 0xC: Interrupt status */
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u32 reserved2;
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u32 ie; /* 0x14: Interrupt enable */
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u32 reserved3[251];
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u32 rcw1; /* 0x404: Rx Configuration Word 1 */
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u32 tc; /* 0x408: Tx Configuration */
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u32 reserved4;
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u32 emmc; /* 0x410: EMAC mode configuration */
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u32 reserved5[59];
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u32 mdio_mc; /* 0x500: MII Management Config */
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u32 mdio_mcr; /* 0x504: MII Management Control */
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u32 mdio_mwd; /* 0x508: MII Management Write Data */
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u32 mdio_mrd; /* 0x50C: MII Management Read Data */
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u32 reserved6[124];
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u32 uaw0; /* 0x700: Unicast address word 0 */
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u32 uaw1; /* 0x704: Unicast address word 1 */
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};
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/*
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* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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static inline int mdio_wait(struct eth_device *dev)
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{
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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u32 timeout = 200;
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/* Wait till MDIO interface is ready to accept a new transaction. */
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while (timeout && (!(in_be32(®s->mdio_mcr)
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& XAE_MDIO_MCR_READY_MASK))) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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return 0;
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}
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static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
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u16 *val)
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{
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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u32 mdioctrlreg = 0;
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if (mdio_wait(dev))
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return 1;
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mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
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& XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_READ_MASK;
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out_be32(®s->mdio_mcr, mdioctrlreg);
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if (mdio_wait(dev))
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return 1;
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/* Read data */
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*val = in_be32(®s->mdio_mrd);
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return 0;
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}
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static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
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u32 data)
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{
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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u32 mdioctrlreg = 0;
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if (mdio_wait(dev))
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return 1;
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mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
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& XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_WRITE_MASK;
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/* Write data */
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out_be32(®s->mdio_mwd, data);
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out_be32(®s->mdio_mcr, mdioctrlreg);
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if (mdio_wait(dev))
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return 1;
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return 0;
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}
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/* Setting axi emac and phy to proper setting */
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static int setup_phy(struct eth_device *dev)
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{
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u16 phyreg;
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u32 i, speed, emmc_reg, ret;
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struct axidma_priv *priv = dev->priv;
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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struct phy_device *phydev;
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u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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if (priv->phyaddr == -1) {
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/* Detect the PHY address */
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for (i = 31; i >= 0; i--) {
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ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
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if (!ret && (phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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priv->phyaddr = i;
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debug("axiemac: Found valid phy address, %x\n",
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phyreg);
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break;
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}
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}
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}
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/* Interface - look at tsec */
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
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phydev->supported &= supported;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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if (phy_startup(phydev)) {
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printf("axiemac: could not initialize PHY %s\n",
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phydev->dev->name);
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return 0;
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}
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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switch (phydev->speed) {
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case 1000:
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speed = XAE_EMMC_LINKSPD_1000;
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break;
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case 100:
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speed = XAE_EMMC_LINKSPD_100;
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break;
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case 10:
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speed = XAE_EMMC_LINKSPD_10;
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break;
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default:
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return 0;
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}
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/* Setup the emac for the phy speed */
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emmc_reg = in_be32(®s->emmc);
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emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
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emmc_reg |= speed;
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/* Write new speed setting out to Axi Ethernet */
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out_be32(®s->emmc, emmc_reg);
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/*
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* Setting the operating speed of the MAC needs a delay. There
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* doesn't seem to be register to poll, so please consider this
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* during your application design.
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*/
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udelay(1);
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return 1;
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}
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/* STOP DMA transfers */
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static void axiemac_halt(struct eth_device *dev)
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{
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struct axidma_priv *priv = dev->priv;
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u32 temp;
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/* Stop the hardware */
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temp = in_be32(&priv->dmatx->control);
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temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
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out_be32(&priv->dmatx->control, temp);
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temp = in_be32(&priv->dmarx->control);
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temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
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out_be32(&priv->dmarx->control, temp);
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debug("axiemac: Halted\n");
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}
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static int axi_ethernet_init(struct eth_device *dev)
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{
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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u32 timeout = 200;
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/*
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* Check the status of the MgtRdy bit in the interrupt status
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* registers. This must be done to allow the MGT clock to become stable
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* for the Sgmii and 1000BaseX PHY interfaces. No other register reads
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* will be valid until this bit is valid.
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* The bit is always a 1 for all other PHY interfaces.
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*/
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while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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/* Stop the device and reset HW */
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/* Disable interrupts */
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out_be32(®s->ie, 0);
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/* Disable the receiver */
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out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
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/*
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* Stopping the receiver in mid-packet causes a dropped packet
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* indication from HW. Clear it.
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*/
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/* Set the interrupt status register to clear the interrupt */
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out_be32(®s->is, XAE_INT_RXRJECT_MASK);
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/* Setup HW */
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/* Set default MDIO divisor */
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out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
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debug("axiemac: InitHw done\n");
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return 0;
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}
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static int axiemac_setup_mac(struct eth_device *dev)
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{
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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/* Set the MAC address */
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int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
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(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
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out_be32(®s->uaw0, val);
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val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
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val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
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out_be32(®s->uaw1, val);
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return 0;
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}
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/* Reset DMA engine */
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static void axi_dma_init(struct eth_device *dev)
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{
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struct axidma_priv *priv = dev->priv;
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u32 timeout = 500;
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/* Reset the engine so the hardware starts from a known state */
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out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
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out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
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/* At the initialization time, hardware should finish reset quickly */
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while (timeout--) {
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/* Check transmit/receive channel */
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/* Reset is done when the reset bit is low */
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if (!(in_be32(&priv->dmatx->control) |
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in_be32(&priv->dmarx->control))
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& XAXIDMA_CR_RESET_MASK) {
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break;
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}
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}
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if (!timeout)
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printf("%s: Timeout\n", __func__);
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}
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static int axiemac_init(struct eth_device *dev, bd_t * bis)
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{
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struct axidma_priv *priv = dev->priv;
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struct axi_regs *regs = (struct axi_regs *)dev->iobase;
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u32 temp;
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debug("axiemac: Init started\n");
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/*
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* Initialize AXIDMA engine. AXIDMA engine must be initialized before
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* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
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* reset, and since AXIDMA reset line is connected to AxiEthernet, this
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* would ensure a reset of AxiEthernet.
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*/
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axi_dma_init(dev);
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/* Initialize AxiEthernet hardware. */
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if (axi_ethernet_init(dev))
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return -1;
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/* Disable all RX interrupts before RxBD space setup */
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temp = in_be32(&priv->dmarx->control);
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temp &= ~XAXIDMA_IRQ_ALL_MASK;
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out_be32(&priv->dmarx->control, temp);
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/* Start DMA RX channel. Now it's ready to receive data.*/
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out_be32(&priv->dmarx->current, (u32)&rx_bd);
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/* Setup the BD. */
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memset(&rx_bd, 0, sizeof(rx_bd));
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rx_bd.next = (u32)&rx_bd;
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rx_bd.phys = (u32)&rxframe;
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rx_bd.cntrl = sizeof(rxframe);
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/* Flush the last BD so DMA core could see the updates */
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flush_cache((u32)&rx_bd, sizeof(rx_bd));
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/* It is necessary to flush rxframe because if you don't do it
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* then cache can contain uninitialized data */
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flush_cache((u32)&rxframe, sizeof(rxframe));
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/* Start the hardware */
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temp = in_be32(&priv->dmarx->control);
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temp |= XAXIDMA_CR_RUNSTOP_MASK;
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out_be32(&priv->dmarx->control, temp);
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/* Rx BD is ready - start */
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out_be32(&priv->dmarx->tail, (u32)&rx_bd);
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/* Enable TX */
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out_be32(®s->tc, XAE_TC_TX_MASK);
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/* Enable RX */
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out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
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/* PHY setup */
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if (!setup_phy(dev)) {
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axiemac_halt(dev);
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return -1;
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}
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debug("axiemac: Init complete\n");
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return 0;
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}
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static int axiemac_send(struct eth_device *dev, void *ptr, int len)
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{
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struct axidma_priv *priv = dev->priv;
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u32 timeout;
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if (len > PKTSIZE_ALIGN)
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len = PKTSIZE_ALIGN;
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/* Flush packet to main memory to be trasfered by DMA */
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flush_cache((u32)ptr, len);
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/* Setup Tx BD */
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memset(&tx_bd, 0, sizeof(tx_bd));
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/* At the end of the ring, link the last BD back to the top */
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tx_bd.next = (u32)&tx_bd;
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tx_bd.phys = (u32)ptr;
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/* Save len */
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tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
|
|
XAXIDMA_BD_CTRL_TXEOF_MASK;
|
|
|
|
/* Flush the last BD so DMA core could see the updates */
|
|
flush_cache((u32)&tx_bd, sizeof(tx_bd));
|
|
|
|
if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
|
|
u32 temp;
|
|
out_be32(&priv->dmatx->current, (u32)&tx_bd);
|
|
/* Start the hardware */
|
|
temp = in_be32(&priv->dmatx->control);
|
|
temp |= XAXIDMA_CR_RUNSTOP_MASK;
|
|
out_be32(&priv->dmatx->control, temp);
|
|
}
|
|
|
|
/* Start transfer */
|
|
out_be32(&priv->dmatx->tail, (u32)&tx_bd);
|
|
|
|
/* Wait for transmission to complete */
|
|
debug("axiemac: Waiting for tx to be done\n");
|
|
timeout = 200;
|
|
while (timeout && (!in_be32(&priv->dmatx->status) &
|
|
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
|
|
timeout--;
|
|
udelay(1);
|
|
}
|
|
if (!timeout) {
|
|
printf("%s: Timeout\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
debug("axiemac: Sending complete\n");
|
|
return 0;
|
|
}
|
|
|
|
static int isrxready(struct eth_device *dev)
|
|
{
|
|
u32 status;
|
|
struct axidma_priv *priv = dev->priv;
|
|
|
|
/* Read pending interrupts */
|
|
status = in_be32(&priv->dmarx->status);
|
|
|
|
/* Acknowledge pending interrupts */
|
|
out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
|
|
|
|
/*
|
|
* If Reception done interrupt is asserted, call RX call back function
|
|
* to handle the processed BDs and then raise the according flag.
|
|
*/
|
|
if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axiemac_recv(struct eth_device *dev)
|
|
{
|
|
u32 length;
|
|
struct axidma_priv *priv = dev->priv;
|
|
u32 temp;
|
|
|
|
/* Wait for an incoming packet */
|
|
if (!isrxready(dev))
|
|
return 0;
|
|
|
|
debug("axiemac: RX data ready\n");
|
|
|
|
/* Disable IRQ for a moment till packet is handled */
|
|
temp = in_be32(&priv->dmarx->control);
|
|
temp &= ~XAXIDMA_IRQ_ALL_MASK;
|
|
out_be32(&priv->dmarx->control, temp);
|
|
|
|
length = rx_bd.app4 & 0xFFFF; /* max length mask */
|
|
#ifdef DEBUG
|
|
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
|
|
#endif
|
|
/* Pass the received frame up for processing */
|
|
if (length)
|
|
net_process_received_packet(rxframe, length);
|
|
|
|
#ifdef DEBUG
|
|
/* It is useful to clear buffer to be sure that it is consistent */
|
|
memset(rxframe, 0, sizeof(rxframe));
|
|
#endif
|
|
/* Setup RxBD */
|
|
/* Clear the whole buffer and setup it again - all flags are cleared */
|
|
memset(&rx_bd, 0, sizeof(rx_bd));
|
|
rx_bd.next = (u32)&rx_bd;
|
|
rx_bd.phys = (u32)&rxframe;
|
|
rx_bd.cntrl = sizeof(rxframe);
|
|
|
|
/* Write bd to HW */
|
|
flush_cache((u32)&rx_bd, sizeof(rx_bd));
|
|
|
|
/* It is necessary to flush rxframe because if you don't do it
|
|
* then cache will contain previous packet */
|
|
flush_cache((u32)&rxframe, sizeof(rxframe));
|
|
|
|
/* Rx BD is ready - start again */
|
|
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
|
|
|
|
debug("axiemac: RX completed, framelength = %d\n", length);
|
|
|
|
return length;
|
|
}
|
|
|
|
static int axiemac_miiphy_read(const char *devname, uchar addr,
|
|
uchar reg, ushort *val)
|
|
{
|
|
struct eth_device *dev = eth_get_dev();
|
|
u32 ret;
|
|
|
|
ret = phyread(dev, addr, reg, val);
|
|
debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
|
|
return ret;
|
|
}
|
|
|
|
static int axiemac_miiphy_write(const char *devname, uchar addr,
|
|
uchar reg, ushort val)
|
|
{
|
|
struct eth_device *dev = eth_get_dev();
|
|
|
|
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
|
|
return phywrite(dev, addr, reg, val);
|
|
}
|
|
|
|
static int axiemac_bus_reset(struct mii_dev *bus)
|
|
{
|
|
debug("axiemac: Bus reset\n");
|
|
return 0;
|
|
}
|
|
|
|
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
|
|
unsigned long dma_addr)
|
|
{
|
|
struct eth_device *dev;
|
|
struct axidma_priv *priv;
|
|
|
|
dev = calloc(1, sizeof(struct eth_device));
|
|
if (dev == NULL)
|
|
return -1;
|
|
|
|
dev->priv = calloc(1, sizeof(struct axidma_priv));
|
|
if (dev->priv == NULL) {
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
priv = dev->priv;
|
|
|
|
sprintf(dev->name, "aximac.%lx", base_addr);
|
|
|
|
dev->iobase = base_addr;
|
|
priv->dmatx = (struct axidma_reg *)dma_addr;
|
|
/* RX channel offset is 0x30 */
|
|
priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
|
|
dev->init = axiemac_init;
|
|
dev->halt = axiemac_halt;
|
|
dev->send = axiemac_send;
|
|
dev->recv = axiemac_recv;
|
|
dev->write_hwaddr = axiemac_setup_mac;
|
|
|
|
#ifdef CONFIG_PHY_ADDR
|
|
priv->phyaddr = CONFIG_PHY_ADDR;
|
|
#else
|
|
priv->phyaddr = -1;
|
|
#endif
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
|
|
miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
priv->bus->reset = axiemac_bus_reset;
|
|
#endif
|
|
return 1;
|
|
}
|