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7c45fc9870
Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
16 lines
323 B
Plaintext
16 lines
323 B
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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config SIFIVE_FU540
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bool
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select ARCH_EARLY_INIT_R
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER
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imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply CMD_CPU
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imply SPL_CPU_SUPPORT
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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