mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-18 00:57:59 +09:00
7bf82cc1f8
When the boot of J721E devices using the primary bootmode (configured via device pins) fails a boot using the configured backup bootmode is attempted. To take advantage of the backup boot mode feature go ahead and add support to the J721E init code to determine whether the ROM code performed the boot using the primary or backup boot mode, and if booted from the backup boot mode, decode the bootmode settings into the appropriate U-Boot mode accordingly so that the boot can proceed. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: J721E SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_J721E_HARDWARE_H
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#define __ASM_ARCH_J721E_HARDWARE_H
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#include <config.h>
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
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#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
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#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
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* shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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/* MCU SCRATCHPAD usage */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
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#endif /* __ASM_ARCH_J721E_HARDWARE_H */
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