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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/*
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* (C) Copyright 2007, Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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********************************************************************
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* NOTE: This header file defines an interface to U-Boot. Including
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* this (unmodified) header file in another file is considered normal
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* use of U-Boot, and does *not* fall under the heading of "derived
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* work".
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********************************************************************
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*/
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#ifndef _XTENSA_U_BOOT_H
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#define _XTENSA_U_BOOT_H
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#ifdef CONFIG_SYS_GENERIC_BOARD
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/* Use the generic board which requires a unified bd_info */
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#include <asm-generic/u-boot.h>
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#else
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#ifndef __ASSEMBLY__
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typedef struct bd_info {
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int bi_baudrate; /* serial console baudrate */
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unsigned long bi_ip_addr; /* IP Address */
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unsigned char bi_enetaddr[6]; /* Ethernet adress */
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unsigned long bi_boot_params; /* where this board expects params */
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unsigned long bi_memstart; /* start of DRAM memory VA */
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unsigned long bi_memsize; /* size of DRAM memory in bytes */
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unsigned long bi_flashstart; /* start of FLASH memory */
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unsigned long bi_flashsize; /* size of FLASH memory */
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unsigned long bi_flashoffset; /* offset to skip UBoot image */
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} bd_t;
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#endif /* __ ASSEMBLY__ */
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#endif /* CONFIG_SYS_GENERIC_BOARD */
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/* For image.h:image_check_target_arch() */
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#define IH_ARCH_DEFAULT IH_ARCH_XTENSA
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#endif /* _XTENSA_U_BOOT_H */
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