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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
21 lines
359 B
C
21 lines
359 B
C
/*
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* (C) Copyright 2007, Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_GBL_DATA_H
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#define _XTENSA_GBL_DATA_H
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/* Architecture-specific global data */
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struct arch_global_data {
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unsigned long cpu_clk;
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd
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#endif /* _XTENSA_GBL_DATA_H */
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