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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/*
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* Definition of the Linux/Xtensa boot parameter structure
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*
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* Copyright (C) 2001 - 2009 Tensilica Inc.
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*
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* (Concept borrowed from the 68K port)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_BOOTPARAM_H
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#define _XTENSA_BOOTPARAM_H
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#define BP_VERSION 0x0001
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#define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/
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#define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */
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#define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */
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#define BP_TAG_SERIAL_BAUDRATE 0x1004 /* baud rate of current console */
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#define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */
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#define BP_TAG_FDT 0x1006 /* flat device tree */
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#define BP_TAG_FIRST 0x7B0B /* first tag with a version number */
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#define BP_TAG_LAST 0x7E0B /* last tag */
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#ifndef __ASSEMBLY__
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/* All records are aligned to 4 bytes */
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struct bp_tag {
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unsigned short id; /* tag id */
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unsigned short size; /* size of this record excluding the structure*/
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unsigned long data[0]; /* data */
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};
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#define bp_tag_next(tag) \
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((struct bp_tag *)((unsigned long)((tag) + 1) + (tag)->size))
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struct meminfo {
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unsigned long type;
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unsigned long start;
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unsigned long end;
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};
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#define MEMORY_TYPE_CONVENTIONAL 0x1000
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#define MEMORY_TYPE_NONE 0x2000
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struct sysmem_info {
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int nr_banks;
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struct meminfo bank[0];
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};
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#endif
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#endif
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