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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
37 lines
830 B
C
37 lines
830 B
C
/*
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* Copyright (C) 2001 - 2012 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_BITOPS_H
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#define _XTENSA_BITOPS_H
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#include <asm/system.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/__ffs.h>
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static inline int test_bit(int nr, const void *addr)
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{
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return ((unsigned char *)addr)[nr >> 3] & (1u << (nr & 7));
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}
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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unsigned long flags;
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unsigned char tmp;
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unsigned char mask = 1u << (nr & 7);
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local_irq_save(flags);
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tmp = ((unsigned char *)addr)[nr >> 3];
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((unsigned char *)addr)[nr >> 3] |= mask;
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local_irq_restore(flags);
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return tmp & mask;
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}
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#endif /* _XTENSA_BITOPS_H */
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