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https://github.com/brain-hackers/u-boot-brain
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da188a0388
DC232B is an xtensa processor with full MMUv2 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
122 lines
4.2 KiB
C
122 lines
4.2 KiB
C
/*
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* This header file contains assembly-language definitions (assembly
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* macros, etc.) for this specific Xtensa processor's TIE extensions
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* and options. It is customized to this Xtensa processor configuration.
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* This file is autogenerated, please do not edit.
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*
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* Copyright (C) 1999-2007 Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-8, 4, 4
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rsr \at1, ACCLO // MAC16 accumulator
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rsr \at2, ACCHI
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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s32i \at2, \ptr, .Lxchal_ofs_ + 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-16, 4, 4
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rsr \at1, M0 // MAC16 registers
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rsr \at2, M1
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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s32i \at2, \ptr, .Lxchal_ofs_ + 4
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rsr \at1, M2
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rsr \at2, M3
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s32i \at1, \ptr, .Lxchal_ofs_ + 8
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s32i \at2, \ptr, .Lxchal_ofs_ + 12
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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rsr \at1, SCOMPARE1 // conditional store option
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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rur \at1, THREADPTR // threadptr option
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s32i \at1, \ptr, .Lxchal_ofs_ + 0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm // xchal_ncp_store
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-8, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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l32i \at2, \ptr, .Lxchal_ofs_ + 4
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wsr \at1, ACCLO // MAC16 accumulator
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wsr \at2, ACCHI
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-16, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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l32i \at2, \ptr, .Lxchal_ofs_ + 4
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wsr \at1, M0 // MAC16 registers
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wsr \at2, M1
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l32i \at1, \ptr, .Lxchal_ofs_ + 8
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l32i \at2, \ptr, .Lxchal_ofs_ + 12
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wsr \at1, M2
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wsr \at2, M3
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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wsr \at1, SCOMPARE1 // conditional store option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
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xchal_sa_align \ptr, 0, 1024-4, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_ + 0
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wur \at1, THREADPTR // threadptr option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 2
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#define XCHAL_SA_NUM_ATMPS 2
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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