Thierry Reding aba11d4476 ARM: tegra124: Clear IDDQ when enabling PLLC ... Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2015-09-16 16:11:31 -07:00
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ahb.h
clock-tables.h	ARM: tegra: Implement clk_m	2015-09-16 16:10:22 -07:00
clock.h	ARM: tegra124: Clear IDDQ when enabling PLLC	2015-09-16 16:11:31 -07:00
display.h	tegra: video: support eDP displays on Tegra124 devices	2015-05-13 09:24:11 -07:00
flow.h	tegra: Introduce SRAM repair on tegra124	2015-06-09 09:56:14 -07:00
funcmux.h
gp_padctrl.h
gpio.h
mc.h	ARM: tegra: Enable SMMU when going non-secure	2015-05-13 09:24:16 -07:00
pinmux.h
pmu.h
powergate.h
pwm.h	tegra: Move the pwm into tegra-common	2015-05-13 09:24:06 -07:00
sysctr.h
tegra.h